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    GAL 16 V 8 D DIP Search Results

    GAL 16 V 8 D DIP Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    7M2-122 Coilcraft Inc Variable Inductor, 1.1uH Min, 1.3uH Max, Ferrite-Core, Shielded, 3030, DIP-5 Visit Coilcraft Inc
    7M2-272 Coilcraft Inc Variable Inductor, 2.4uH Min, 3uH Max, Ferrite-Core, Shielded, 3030, DIP-5 Visit Coilcraft Inc
    7M2-561 Coilcraft Inc Variable Inductor, 0.526uH Min, 0.594uH Max, Ferrite-Core, Shielded, 3030, DIP-5 Visit Coilcraft Inc
    7M3-103 Coilcraft Inc Variable Inductor, 8uH Min, 12uH Max, Ferrite-Core, Shielded, 3030, DIP-5 Visit Coilcraft Inc
    7M3-182 Coilcraft Inc Variable Inductor, 1.4uH Min, 2.2uH Max, Ferrite-Core, Shielded, 3030, DIP-5 Visit Coilcraft Inc

    GAL 16 V 8 D DIP Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    FEP321

    Abstract: ABB Fep311 FEP311 FET321 FEP300 FEP321 flow meter FEP315 FET301 FET325 ABB FEP315
    Text: Data Sheet DS/FEP300-EN Electromagnetic Flowmeter ProcessMaster FEP300 Intuitive operation - Softkey-based functionality - “Easy Set-up” function Non-contact buttons - Parameterization of the device without the need to open the housing Diagnostics for real-life situations


    Original     		DS/FEP300-EN FEP300 3KXF081100L0001 3KXF231300R1001 DS/FEP300-EN FEP321 ABB Fep311 FEP311 FET321 FEP300 FEP321 flow meter FEP315 FET301 FET325 ABB FEP315 PDF

    lm555 timer circuit

    Abstract: g22v10 GAL G22V10 CON40A LM555 video pattern generator 386SX DK65550 GAL22V10 weitek
    Text: 65550/554 Suggested ZV Port Manufacturing Test via the PCMCIA Socket Application Note Revision 1.1 June 1996 P R E L I M I N A R Y  Copyright Notice Copyright 1996 Chips and Technologies, Inc. ALL RIGHTS RESERVED. This manual is copyrighted by Chips and Technologies, Inc. You may not reproduce, transmit,


    Original     		PDF

    FEP321

    Abstract: FEP521 FEP511 FET321 2501 optocoupler FET521 B1647 FEP500 F304L sensor tv 1453
    Text: Data Sheet DS/FEP500-EN Electromagnetic Flowmeter ProcessMaster FEP500 Intuitive operation - Softkey-based functionality - “Easy Set-up” function Diagnostics for real-life situations - Status messages in accordance with NAMUR - Help texts in the display


    Original     		DS/FEP500-EN FEP500 state0789 3KXF081100L0001 3KXF231500R1001 FEP321 FEP521 FEP511 FET321 2501 optocoupler FET521 B1647 FEP500 F304L sensor tv 1453 PDF

    FEH511

    Abstract: FEP321 FEH521 FET501 2501 optocoupler FET521 3KXF081100L0001 FET321 JIS B2210 DIN 32676 iso 2037
    Text: Data Sheet DS/FEH500-EN Electromagnetic Flowmeter HygienicMaster FEH500 Intuitive operation - Softkey-based functionality - “Easy Set-up” function Diagnostics for real-life situations - Status messages in accordance with NAMUR - Help texts in the display


    Original     		DS/FEH500-EN FEH500 technolo0789 3KXF081100L0001 3KXF232500R1001 FEH511 FEP321 FEH521 FET501 2501 optocoupler FET521 3KXF081100L0001 FET321 JIS B2210 DIN 32676 iso 2037 PDF

    gal programming algorithm

    Abstract: XOR en TTL gal9 opal GAL20V8Q
    Text: ^ National ÉM Semiconductor NATL SEMICOND M EM ORY NSC3 February 1992 r -v < -/? -0 7 GAL20V8QS 24-Pin Generic Array Logic Family General Description Features The EECMOS GAL QS devices combine a high per­ formance CMOS process with electrically erasable floating


    OCR Scan     		GAL20V8QS 24-Pin gal programming algorithm XOR en TTL gal9 opal GAL20V8Q PDF

    Untitled

    Abstract: No abstract text available
    Text: GAL16V8A-10, -12, -15, -20 National Semiconductor GAL16V8A-10, -12, -15, -20 Generic Array Logic General Description Features The NSC E2CMOS GAL device combines a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology


    OCR Scan     		GAL16V8A-10, 20-pin GAL16V8A 20-pin TL/L/9999-32 PDF

    gal 16v8 programming specification

    Abstract: gal 16v8 programming algorithm National SEMICONDUCTOR GAL16V8 gal16v8 programming algorithm gal16v8 national GAL16V8-25 GAL16V8-20 application GAL 16l8 gal programming gal16v8
    Text: GAL16V8/A 03 National Semiconductor GAL16V8/A 20-Pin Generic Array Logic Family General Description Features The EECMOS GAL 16V8/A devices are fabricated using electrically erasable floating gate technology. This program­ mable memory technology applied to array logic provides


    OCR Scan     		GAL16V8/A GAL16V8/A 20-Pin 16V8/A GAL16V8 8l30l TL/L/11255-21 gal 16v8 programming specification gal 16v8 programming algorithm National SEMICONDUCTOR GAL16V8 gal16v8 programming algorithm gal16v8 national GAL16V8-25 GAL16V8-20 application GAL 16l8 gal programming PDF

    gal programming algorithm

    Abstract: gal programming gal programming specification 6AL16V8A application GAL 16l8 16L8* GAL 6AL16 16V8A gal16vba GAL 16 v 8 D DIP
    Text: GAL16V8A-10, -12, -15, -20 mH 5g | National Semiconductor GAL16V8A-10, -12, -15, -20 Generic Array Logic General Description Features The NSC E2CMOStm GAL device combines a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology


    OCR Scan     		GAL16V8A-10, 20-pin GAL16V8A tl/l/9999-32 gal programming algorithm gal programming gal programming specification 6AL16V8A application GAL 16l8 16L8* GAL 6AL16 16V8A gal16vba GAL 16 v 8 D DIP PDF

    gal 16v8 programming algorithm

    Abstract: GAL16V8 application notes gal16v8 national National SEMICONDUCTOR GAL16V8 gal 16v8 programming specification GAL16V8-25 25L90 gal programming algorithm GAL16V8-25L 16L8* GAL
    Text: GAL16V8 National iCA Semiconductor GAL16V8 Generic Array Logic General Description Features The NSC E2CMOS GAL device combines a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology


    OCR Scan     		GAL16V8 GAL16V8 20-pin gal 16v8 programming algorithm GAL16V8 application notes gal16v8 national National SEMICONDUCTOR GAL16V8 gal 16v8 programming specification GAL16V8-25 25L90 gal programming algorithm GAL16V8-25L 16L8* GAL PDF

    gal programming specification

    Abstract: GAL Gate Array Logic GAL20R10 GAL20RA10 gal programming algorithm 20ra10 gal programmer
    Text: GAL20RA10-15, -20, -25 PRELIMINARY National Semiconductor GAL20RA10-15, -20, -25 Generic Array Logic General Description Features The NSC E2CMOStm GAL device combines a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology


    OCR Scan     		GAL20RA10-15, GAL20RA10 TL/L/10775-10 TL/L/10775-11 TL/L/10775-13 TL/L/10775-12 GAL20R10 Tl/l/10775-14 TL/L/10775-15 TL/L/10775-17 gal programming specification GAL Gate Array Logic GAL20R10 gal programming algorithm 20ra10 gal programmer PDF

    Untitled

    Abstract: No abstract text available
    Text: se MIKROn Absolute Maximum Ratings Symbol VcES VcGR lc ICM Values Conditions ' Units Rge = 20 k£2 Tcase = 25/80 °C Tcase = 25/80 °C; tp = 1 ms V ges AC, 1 min. DIN 40 040 DIN IEC 68 T.1 Inverse Diode 8 Tcase = 25/80 °C If = - lc Tcase = 25/80 C . tp = 1 ms


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    S16R6

    Abstract: TDA 2088 GAL16V8Q GAL16V80
    Text: 4 TE National Semiconductor D NSC 3 b S D l i a t i DDbSEl fl T li NATL SEMICOND MEMORY) February1992 T -V * -/? -0 7 GAL16V8QS 20-Pin Generic Array Logic Family General Description Features The EECMOS GAL QS devices combine a high per­ formance CMOS process with electrically erasable floating


    OCR Scan     		February1992 S16R6 TDA 2088 GAL16V8Q GAL16V80 PDF

    GAL16V8QS

    Abstract: 16L8* GAL application GAL 16l8 gal programming specification gal16v8qs25 gal programming algorithm GAL16v8 algorithm
    Text: GAL16V8QS £3 National ÆM Semiconductor GAL16V8QS 20-Pin Generic Array Logic Family General Description Features The EECMOS GAL QS devices combine a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology


    OCR Scan     		GAL16V8QS TL/L/11145-23 GAL16V8QS 16L8* GAL application GAL 16l8 gal programming specification gal16v8qs25 gal programming algorithm GAL16v8 algorithm PDF

    gal22v10 application

    Abstract: GAL22V10 PAL22V10 QAL22V10-30L
    Text: PRELIMINARY GAL22V10 yw \ National mjM Semiconductor GAL22V10, -15, -20, -25, -30 Generic Array Logic General Description Features The NSC E2CMOStm GAL devices combine a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology


    OCR Scan     		GAL22V10, 24-pin GAL22V10 TL/L/10406-20 TL/l/10406-21 gal22v10 application PAL22V10 QAL22V10-30L PDF

    GAL20Vb

    Abstract: GAL20V8QS-15L
    Text: GAL20V8QS 03 National mm Semiconductor GAL20V8QS 24-Pin Generic Array Logic Family General Description Features The EECMOS GAL QS tm devices combine a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology


    OCR Scan     		GAL20V8QS GAL20V8QS 24-Pin GAL20V8QS; 28-lead GAL20Vb GAL20V8QS-15L PDF

    QAL22V10-30L

    Abstract: PAL22V10 GAL22V10 National gal programming algorithm LY1040 GAL22V10 GAL Gate Array Logic
    Text: GAL22V10 NATL SEMICOND LS0112b b3E D MEMORY DGb7b45 «NSCB National mm Semiconductor GAL22V10, -15, -20, -25, -30 Generic Array Logic General Description Features The NSC E2CMOS GAL devices combine a high per­ formance CMOS process with electrically erasable floating


    OCR Scan     		bS0112b D0b7b45 GAL22V10, 24-pin GAL22V10 tl/l/10406-19 tl/l/10406-20 TL/L/10406-21 QAL22V10-30L PAL22V10 GAL22V10 National gal programming algorithm LY1040 GAL Gate Array Logic PDF

    Untitled

    Abstract: No abstract text available
    Text: m GAL22V10, -15, -20, -25, -30 Generic Array Logic General Description Features The NSC E2CMOStm g a l devices combine a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable


    OCR Scan     		GAL22V10, 24-pin GAL22V10 GAL22V10 PDF

    siemens igbt BSM 150 gb 100 d

    Abstract: BSM100GB120D siemens igbt
    Text: bDE D • 023Sb05 OOMSÔÛO 122 ■ S I E G SIEMENS SIEMENS AKTIENGESELLSCHAF ' 7 <23 o ’^ ” BSM 100 GB 120 D BSM 100 GAL 120 D IGBT Module Preliminary Data VCE = 1200 V I c = 2 x 1 3 5 A at r c = 25 'C / c = 2 x 1 0 0 A at r c = 80 C • • • • •


    OCR Scan     		235ti05 2x135 2x100 C67076-A2107-A2 C67076-A2012-A2 siemens igbt BSM 150 gb 100 d BSM100GB120D siemens igbt PDF

    GAL Gate Array Logic

    Abstract: gal22v10 application note gal22v10 application gal22v10
    Text: GAL22V10 EH National m M Semiconductor GAL22V10, -15, -20, -25, -30 Generic Array Logic General Description Features The NSC E2CMOS GAL devices combine a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology


    OCR Scan     		GAL22V10 GAL22V10, 24-pin GAL22V10 architectur10 TL/L/10406-21 GAL Gate Array Logic gal22v10 application note gal22v10 application PDF

    IGBT Module BSM150GB120D

    Abstract: siemens igbt BSM 150 gb 100 d siemens igbt BSM 150 Gb 160 d BSM 15 GB GAL 700 BSM150GB120D siemens igbt BSM 100 gb siemens igbt BSM 50 gb 100 d aa-es siemens
    Text: bOE D • flEBSLGS OOMSâ^b S^T « S I E G SIEMENS SIEMENS AKTIENGESELLSCHAF ^ IGBT Module Preliminary Data 3 - 0 9 BSM150GB120D BSM 150 GAL 120 D V CE = 1200 V I c = 2 X 200 A at Tc = 25 C I c = 2 x 1 5 0 A at r c = 8 0 C • • • • • Power m odule


    OCR Scan     		BSM150GB120D 2x150 C67076-A2108-A2 C67076-A2013-A2 sii00202 IGBT Module BSM150GB120D siemens igbt BSM 150 gb 100 d siemens igbt BSM 150 Gb 160 d BSM 15 GB GAL 700 BSM150GB120D siemens igbt BSM 100 gb siemens igbt BSM 50 gb 100 d aa-es siemens PDF

    26LS232

    Abstract: 8506402QA 8768401MQA 80C31-16 8200802JA 9078101MCA 8856602QA 82S105 59628856601XA 7802001EA
    Text: Philips Semiconductors Military and Special Products Data Handbook Product Listing by Basic Part Number Basic Part Number Military Drawing 5962- Device Description Package Description Basic Part Number Military Drawing 5962- ABT22V10A 91760Ö7MLX BICMOS GAL


    OCR Scan     		ABT22V10A ABT22V10B LM124 LM139 LM139A PLS168 PLS173 26LS232 8506402QA 8768401MQA 80C31-16 8200802JA 9078101MCA 8856602QA 82S105 59628856601XA 7802001EA PDF

    GAL20Vb

    Abstract: GAL20V8-25L GAL20V8 gal20v8-25 GAL programming algorithm 14H6 GAL20VB-25Q pal 16P6 25L90 gal20v8 application
    Text: GAL20V8 CTJ National Semiconductor GAL20V8 Generic Array Logic General Description The NSC E2CMOS GAL device combines a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable


    OCR Scan     		GAL20V8 GAL20V8 24-pin GAL20V8; 26-lead GAL20Vb GAL20V8-25L gal20v8-25 GAL programming algorithm 14H6 GAL20VB-25Q pal 16P6 25L90 gal20v8 application PDF

    Semikron SKM 173D

    Abstract: SK 200 GAR 125 SKM200GB173 B679
    Text: s e m ik r o n Absolute Maximum Ratings S ym bol VcES VcGR lc ICM V a lu e s C o nd itions 1 U nits 1700 1700 2 2 0 /1 5 0 440 / 300 ±20 1250 - 4 0 . . .+150 125 4000 Class F 55/150/56 Rqe = 20 k ii Tease = 25/80 °C Tease ~ 25/80 °C; tp = 1 ms Vges Ptoi


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    Untitled

    Abstract: No abstract text available
    Text: ET INC. Industrial PEEL 18CV8I -10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features Industrial Grade Specifications — V cc = 4.5V to 5.5V, TA = -40°C to +85°C — Reprogrammable 20-pin DIP, PLCC and SOIC packages Architectural Flexibility


    OCR Scan     		18CV8I 20-pin 25MHz PDF