A63A
Abstract: 74LSOO
Text: •Quadruple 2-input Positive AND Gates with Open Collector Outputs IP IN ARRANGEMENT ¡C IR C U IT S C H E M A T IC ^ ) •RECOM M ENDED OPERATING CONDITIONS Symbol min typ max High level output voltage Item VOH - - 5.5 Unit V Low level output current IOL
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QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
A63A
74LSOO
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DIVIDE-BY-256
Abstract: ONU block diagram 74LSOO HD74LS393 a63a
Text: •D u a l 4-bit Binary Counters This circuit contains eight master-slave flip-flops and ad ditional gating to implement tw o individual four-bit counters. The HD74LS393 comprises tw o independent four-bit binary counters each having a clear and a clock input.
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HD74LS393
divide-by-256.
QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
DIVIDE-BY-256
ONU block diagram
74LSOO
a63a
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74LSOO
Abstract: HD74LS490
Text: HD74LS490. This c irc u it d itio n a l contains gating to eigh t master-slave im p le m e n t tw o Dual 4 -b it Decade Counters flip -flo p s ind ividu al 4 -b it and ad I BLOCK DIAGRAM K decade counters. Each decade c o u n te r has ind ividu al clo ck, clear, and
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HD74LS490.
divide-by-100
QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
74LSOO
HD74LS490
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74LSOO
Abstract: HD74LS642 Hitachi Scans-001
Text: ♦ O c ta l Bus Transceivers inverted open-collector outputs This octal bus transceiver is designed fo r asynchronous two-way communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus de pending upon the level at the direction control (D IR ) input. The
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QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
74LSOO
HD74LS642
Hitachi Scans-001
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74LSOO
Abstract: No abstract text available
Text: •Quadruple 2-input Positive NAND Gates with Open Collector Outputs •C IR C U IT S C H E M A T IC ^ ) BPIN ARRANGEMENT ■RECOMMENDED OPERATING CONDITIONS Symbol min typ max High level output voltage y oh - - 5 .5 Low level output c u rre n t IO L - -
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25ial
QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
74LSOO
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74LSOO
Abstract: CI 2210 HD74LSoop
Text: •T rip le 3-input Positive NOR Gates • C IR C U IT S C H E M A T IC ^ B P IN ARRANGEMENT ■ELECTRICAL CHARACTERISTICS ( Ta= - 2 0 - +75°C ) Item S ym bol T e s t C o n d itio n s min typ* m ax V lH 2 .0 - - V lL - - 0 .8 U n it Input v o lta g e V
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-400M
75ial
QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
74LSOO
CI 2210
HD74LSoop
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74LSOO
Abstract: 1S2074
Text: •Q u a d ru p le 2-input Positive N AND Schmitt-triggers •C IR C U IT S C H EM A TIC ^ HPIN ARRANGEMENT ■ELECTRICAL CHARACTERISTICS ( Ta= - 20- + 75”C ) Item Symbol min typ* max Unit Vt + V cc — 5V T e s t Conditions 1.4 1.6 1.9 V Vt ~ V cc — 5V
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-400M,
QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
74LSOO
1S2074
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74LSOO
Abstract: HD74LS367A kl66
Text: HD74LS367A * Hex Bus Drivers non-inverted data outputs with three-state outputs I PIN ARRANGEMENT I CIRCUIT SCHEMATIC D r i v e r se c tio n (1 / 6 ) C o n t r o l se c tio n Ootpu Control Ci ~ï7 ]vVcc — 1Output Cont roi Ci 'vLLKy L jc t-E I 6 " Y r]D *
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HD74LS367A*
QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
74LSOO
HD74LS367A
kl66
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ATML U 010
Abstract: ATML H 010 1S2074 400M 74LSOO HD74LS139 OG-16 L400M ATML 010
Text: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The H D74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM
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HD74LS139
QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
ATML U 010
ATML H 010
1S2074
400M
74LSOO
OG-16
L400M
ATML 010
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HD74LSoop
Abstract: 1S2074 74LSOO HD74LS195A Hitachi Scans-001 Scans-0014928
Text: H D 74 L S 19 5A . 4-b¡t Parallel-Access Shift Registers This 4-bit register features parallel inputs, parallel outputs. is loaded into the associated flip-flop and appears at the out puts after the positive transition of the clock input. During loading, serial data flow is inhibited. Shifting is accomplished
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HD74LS195A.
QQ14CI14
DG-14
06max
20-iu8
OG-16
DG-24
HD74LSoop
1S2074
74LSOO
HD74LS195A
Hitachi Scans-001
Scans-0014928
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Untitled
Abstract: No abstract text available
Text: •Quadruple 2-input High-voltage Interface Positive NAND Gates • C IR C U IT SC H EM A TIC O ^ B P IN ARRANGEMENT ■RECOM M ENDED OPERATING CONDITIONS Item S ym bol High lev e l o u tp u t v o lta g e Voh L ow lev el o u tp u t c u r r e n t min ty p
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74LSOO
ib203
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Untitled
Abstract: No abstract text available
Text: •D u a l 4-input Positive AND Gates •PIN ARRANGEMENT ICIRCUIT SCHEMATICO^ ■ELECTRICAL CHARACTERISTICS Item Input voltage O utput voltage Symbol VlH VlL VOH V>L I ih It L ¡1 Input c u rren t S h o rt-c irc u it output c u rren t Supply c u rren t Input clam p voltage
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T-90-10
74LSOO
ib203
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74LSOO
Abstract: HD74LS374 HD74LSoop
Text: HD74LS374 • O c t a l D-type Edge-triggered Flip-Flops with th ree-state IP IN ARRANGEM ENT The H D74LS374, 8-bit registers features totem-pole threestate outputs designed specifically for driving highly-capacitive or relatively iow-impedance loads. The high-impedance third
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HD74LS374,
QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
81mlx
74LSOO
HD74LS374
HD74LSoop
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1S2074
Abstract: 74LSOO HD74LS75 Hitachi Scans-001
Text: •Q uad ru ple Bistable Latches The H D 74LS75 is ideally suited for use as temporary storage for binary information between processing units and input/ • P IN ARRANGEMENT output or indicator units. Information present at a data D input is transferred to the Q output when the enable (G) is
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HD74LS75
T-90-10
ib203
1S2074
74LSOO
Hitachi Scans-001
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HD74LSoop
Abstract: 74LSOO 400M HD74LS54 Hitachi Scans-001
Text: •4 -w id e 2-input, 3-input AND-OR-INVERT Gates • C IR C U IT SCHEM ATIC B P IN ARRANGEMENT N ote The schem atic w ith in the dashed line is included the half inp ut term inals o f H D 7 4 L S 5 4 . ■ELECTRICAL CHARACTERISTICS T a = - 20- + 75°C )
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HD74LS54.
QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
HD74LSoop
74LSOO
400M
HD74LS54
Hitachi Scans-001
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74LSOOP
Abstract: 74LSOO
Text: HD74LS21 •D u al 4-input Positive AND Gates •PIN ARRANGEMENT ¡CIRCU IT SCHEMATICO^ ■ ELECTRICAL CH A RA CTERISTICS Item Symbol Input voltage VlL I6i IlH Input current IlL ¡1 Short-circuit output current Supply current Input clamp voltage * T est Conditions
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-400M
QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
74LSOOP
74LSOO
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DP 804 C
Abstract: JV3 diode 74LSOO HD74LS221
Text: HD74LS221 »Dual Monostable Multivibrators This multivibrator features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a particular voltage level and is not directly related to the tran
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HD74LS221
QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
DP 804 C
JV3 diode
74LSOO
HD74LS221
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74LSOO
Abstract: 74LSOO AND gate
Text: •Quadruple 2-input Exclus¡ve-OR Gates with open collector outputs • P IN ARRANGEMENT ■FUNCTION TABLE Output Inputs Y A B L L L L H H H L H H H L H ; high level, L ; low level, X ; irrelevant. ■RECOMMENDED OPERATING CONDITIONS Symbol min typ max
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QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
74LSOO
74LSOO AND gate
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74LSOO
Abstract: HD74LS390 Hitachi Scans-001
Text: • Dual Decade Counters I BLOCK DIAGRAM {'A This circuit contains eight master-slave flip-flops and ad ditional gating to implement two individual four-bit counters. The H D 74LS390 incorporates dual divide-by-two and divideby-five counters, which can be used to implement cycle
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HD74LS390
divide-by-100.
QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
74LSOO
Hitachi Scans-001
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HD74LSoop
Abstract: 74LSOO
Text: •D u a l 4-input Positive NAND Gates with Open Collector Outputs •C IR C U IT S C H E M A T IC ^ ) « P IN ARRANGEMENT ■RECOMMENDED OPERATING CONDITIONS Item High level output voltage Low leve) output current Symbol min - VoH ÌO L ■ELECTRICAL CHARACTERISTICS (
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QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
HD74LSoop
74LSOO
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HD74LSoop
Abstract: No abstract text available
Text: H D 74L S 164 • 8 - B it Parallel-Out Serial-ln Shift Registers IP IN ARRANGEMENT This 8-bit shift register features gated serial inputs and an asynchronous clear. The gated serial inputs A and B permit complete control over incoming data as a low at either (or
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HD74LS164
T-90-10
74LSOO
ib203
HD74LSoop
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D74LS175
Abstract: 74LS174 example S174H HD74LSoop 74ls175
Text: H D 74LS174/H D74LS175 •H e x Quadrupte D-type Rip-Hops with clear IBLOCK DIAGRAM These positive-edge-triggered flip-flops utilize T T L circuitry to implement D-type flip-flop logic. A ll have a direct clear input, and the H D74LS175 features complementary outputs
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HD74LS174
HD74LS175
D74LS175
T-90-10
74LSOO
ib203
74LS174 example
S174H
HD74LSoop
74ls175
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Untitled
Abstract: No abstract text available
Text: •Q uad ru ple 2-input Exclusive-OR Gates •FU N C TIO N TABLE ■ P IN ARRANGEMENT O u tp u t In p u ts A B Y L L L L H H H L H H H L H ; high level, L ; low level ■ELECTRICAL CHARACTERISTICS Ta= - 2 0 - + 75°C Item S ym bol T e s t C o n d itio n s
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T-90-10
ib203
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74LSOOP
Abstract: No abstract text available
Text: HD74LS02 •Quadruple 2-input Positive NOR Gates ICIR CU IT SCHEMATICO^ IPIN ARRANGEMENT • ELECTRICAL CH ARACTERISTICS T a = -2 0 ~ +75°C ) Item Symbol T est Conditions min typ* VlH 2 .0 - - V VlL _ - 0 .8 V V Input voltage VOH Vcc —4 .7 5 V, V/l = 0 . 8 V , / oh= - 4 0 0 M
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HD74LS02
T-90-10
ib203
74LSOOP
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