hdlc
Abstract: 806C MC68360
Text: MOTOROLA SEMICONDUCTOR TECHNICAL INFORMATION Asynchronous HDLC MC68360 ASYNC HDLC Protocol Microcode User’s Manual Rev 1.1 January 24, 1996 Asynchronous HDLC Asynchronous HDLC 1 ASYNC HDLC Controller Overview 4 2 ASYNC HDLC Controller Key Features 2.1 ASYNC HDLC Channel Frame Transmission Processing
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MC68360
hdlc
806C
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4ppm protocol
Abstract: CRC-16 CRC32 MC68160 MPC823 CRC-CCITT 0xFFFF 0XFFF0000 IrDA Protocol
Text: Communication Processor Module 16.9.18.5 SCC2 APPLETALK PROGRAMMING EXAMPLE. Except for the previously discussed register programming, use the example in Section 16.9.16.14 SCC2 HDLC Programming Example #1. 16.9.19 The SCC2 in Asynchronous HDLC Mode SCC2 Asynchronous HDLC is a frame-based protocol that uses HDLC framing techniques in
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MPC823
MPC823
10BASE-T)
MPC823,
10BASE-T
MC68160
4ppm protocol
CRC-16
CRC32
CRC-CCITT 0xFFFF
0XFFF0000
IrDA Protocol
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PDF
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2RD6
Abstract: RB35 TDNB0
Text: BACK HDLC Device HDLC Controller TXC-05101C DATA SHEET Preliminary FEATURES DESCRIPTION • HDLC ISO/OSI level 2 functions, including internal flag, abort, and zero deletion/insertion The TranSwitch TXC-05101C is a high speed, High Level Data Link Controller HDLC designed to send
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TXC-05101C
CRC-16
CRC-32
36-bit
TXC-05101C-MB
2RD6
RB35
TDNB0
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PDF
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RB35
Abstract: TB28 hdlc CRC16 CRC-16 CRC-32 TB31 TB32 RXB 17-18
Text: HDLC Device HDLC Controller TXC-05101C DATA SHEET Preliminary FEATURES DESCRIPTION • HDLC ISO/OSI level 2 functions, including internal flag, abort, and zero deletion/insertion The TranSwitch TXC-05101C is a high speed, High Level Data Link Controller HDLC designed to send
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TXC-05101C
TXC-05101C
TXC-05101C-MB
RB35
TB28
hdlc
CRC16
CRC-16
CRC-32
TB31
TB32
RXB 17-18
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PDF
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gapped
Abstract: AN392 APP392 DS31256 TS24 E1 frame
Text: Maxim > App Notes > TELECOM Keywords: gapped clock, hdlc controller, HDLC Nov 21, 2002 APPLICATION NOTE 392 DS31256 Gapped Clock Applications Abstract: This application note discusses how to realize gapped clock applications with the DS31256 HDLC Controller.
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DS31256
DS31256.
DS31256,
256-channel
com/an392
DS31256:
AN392,
gapped
AN392
APP392
TS24
E1 frame
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PDF
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Bi-phase-L Coding
Abstract: CRC16 D555 MPC821 manchester differential
Text: Communication Processor Module 16.14 SERIAL COMMUNICATION CONTROLLERS The following is a list of the SCCs’ important features: • Implements HDLC/SDLC, HDLC bus, asynchronous HDLC, BISYNC, synchronous start/stop, asynchronous start/stop UART , AppleTalk/LocalTalk, and totally
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10-Mbps
MPC821
Bi-phase-L Coding
CRC16
D555
manchester differential
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PDF
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MPC821
Abstract: No abstract text available
Text: Communication Processor Module 16.14.19.2 ASYNC HDLC CHANNEL FRAME TRANSMISSION PROCESSING. The ASYNC HDLC controller is designed to work with a minimum amount of intervention from the CPU core. It operates in a similar fashion to the HDLC controller on the MPC821.
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MPC821.
MPC821
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processor 80386
Abstract: Motorola 68020 "network interface controller"
Text: Multichannel Network Interface Controller for HDLC MUNICH32 General Description The Multichannel Network Interface Controller for HDLC (MUNICH32, PEB 20320) is a multichannel protocol controller which handles up to 32 data channels of a fullduplex PCM highway. It performs layer-2 HDLC formatting/
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MUNICH32)
MUNICH32,
MUNICH32
processor 80386
Motorola 68020
"network interface controller"
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PDF
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hdlc
Abstract: CRC16 STS-48 WA01 WA02 NORTEL OC-12 "watermark" WA03
Text: Preliminary Data Sheet WA02 A high-density HDLC communications processor Highlights Introduction * Supports up to 1024-channel HDLC processing for four channelized, unchannelized or transparent DS3/E3s The Nortel Networks WA02 is a highdensity, multi-channel HDLC Highlevel Data Link Control
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1024-channel
hdlc
CRC16
STS-48
WA01
WA02
NORTEL OC-12
"watermark"
WA03
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PDF
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hdlc
Abstract: ITA03968 MUNICH32 80386 microprocessor block diagram Motorola 68020 "network interface controller"
Text: Multichannel Network Interface Controller for HDLC MUNICH32 PEB 20320 General Description The Multichannel Network Interface Controller for HDLC (MUNICH32, PEB 20320) is a multichannel protocol controller which handles up to 32 data channels of a fullduplex PCM highway. It performs layer-2 HDLC formatting/
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MUNICH32)
20320-H
P-MQFP-160-1
80-bit
ITA03968
hdlc
ITA03968
MUNICH32
80386 microprocessor block diagram
Motorola 68020
"network interface controller"
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PDF
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B15C
Abstract: d0415 TB-33 RB35
Text: HDLC Device HDLC Controller, 36-bit Terminal I/O TXC-05101 DATA SHEET Preliminary . FEATURES = = = = = ¿ ^ - 1 - -— DESCRIPTION = • HDLC ISO/OSI level 2 functions, including internal flag, abort, and zero deletion/insertion • Operates up to 51.84 Mbit/s STS-1 data rates
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36-bit
TXC-05101
CRC-16
CRC-32
TXC-05101
B15C
d0415
TB-33
RB35
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PDF
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iboc
Abstract: 1001H DS21455 DS21458 DS2155 DS21Q50 DS21Q55 DS26528 DS31256
Text: Maxim > App Notes > TELECOM Keywords: T1, E1, J1, DS2155, DS21Q50, DS21Q55, DS31256, DS26528, HDLC controller, hdlc, Nov 21, 2002 APPLICATION NOTE 390 DS31256 and T1/E1 Interface Abstract: This application note discusses how to connect the DS31256 HDLC Controller to the DS2155, DS21Q55, DS21Q50 and DS26528 in
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DS2155,
DS21Q50,
DS21Q55,
DS31256,
DS26528,
DS31256
DS21Q50
iboc
1001H
DS21455
DS21458
DS2155
DS21Q55
DS26528
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Untitled
Abstract: No abstract text available
Text: HDLC Device HDLC Controller TXC-05101C DATA SHEET Preliminary = DESCRIPTION — The TranSwitch TXC-05101C is a high speed, High Level Data Link Controller HDLC designed to send and receive packets at line rates up to 51.84 Mbit/s using either a nibble, byte-parallel, or serial interface.
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TXC-05101C
TXC-05101C
TXC-03001,
TXC-03401,
TXC-03701,
TXC-03702,
34-Mbit/s
TXC-21043,
RS-232
AN-305:
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PT7A6525
Abstract: PT7A6525J PT7A6525LJ PT7A6525L mc 6526 p pt7a6526je PT7A6525M PT7A6525LJE CD 1517 PT7A65
Text: Data Sheet PT7A6525/6525L/6526 HDLC Controller |
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PT7A6525/6525L/6526
PT7A6526:
modulo-128
PT0017
PT7A6525
PT7A6525J
PT7A6525LJ
PT7A6525L
mc 6526 p
pt7a6526je
PT7A6525M
PT7A6525LJE
CD 1517
PT7A65
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dwa 108 a
Abstract: TP3421 network crad J28A TP3410 TP3451 TP3451J TP3451N tp3057 TE1127.3
Text: TP3451 ADVANCE INFORMATION National Semiconductor TP3451 ISDN HDLC and GCI Controller General Description Features The TP3451 is a microprocessor peripheral communica tions device designed as both a full-duplex HDLC Framing and formatting controller, and a serial GCI General Circuit
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TP3451
64-byte
TL/H/10727-19
TL/H/10727-20
dwa 108 a
TP3421
network crad
J28A
TP3410
TP3451J
TP3451N
tp3057
TE1127.3
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Untitled
Abstract: No abstract text available
Text: HDL C Device HDLC Controller TX C -0 5 1 01 C D A TA S H E E T Preliminary FEATURES DESCRIPTION • HDLC ISO/OSI level 2 functions, including internal flag, abort, and zero deletion/insertion The TranSwitch TXC-05101C is a high speed, High Level Data Link Controller HDLC designed to send
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CRC-16
CRC-32
36-bit
TXC-05101C
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PDF
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CRC-16
Abstract: PT7A6632
Text: Data Sheet PT7A6632 32-Channel HDLC Controller |
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PT7A6632
32-Channel
048Mb/s
PCM-30
PT019
CRC-16
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mc 6526 p
Abstract: PT7A6525 motorola 6526
Text: Data Sheet PT7A6525/6525L/6526 HDLC Controller |
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PT7A6525/6525L/6526
PT7A6526:
modulo-128
PT7A6525/6525L:
PT0017
mc 6526 p
PT7A6525
motorola 6526
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hdlc
Abstract: 806C MC68360 MC68360 microcode ethernet
Text: Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR Freescale Semiconductor, Inc. TECHNICAL INFORMATION Asynchronous HDLC MC68360 ASYNC HDLC Protocol Microcode User’s Manual Rev 1.1 January 24, 1996 For More Information On This Product, Go to: www.freescale.com
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MC68360
hdlc
806C
MC68360 microcode ethernet
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PDF
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motorola 6803
Abstract: No abstract text available
Text: K M National À jÌ Semiconductor ADVANCE INFORMATION TP3451 ISDN HDLC and GCI Controller General Description Features The TP3451 is a microprocessor peripheral communica tions device designed as both a full-duplex HDLC Framing and formatting controller, and a serial GCI General Circuit
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TP3451
64-byte
TP3451
TL/H/10727-18
motorola 6803
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PDF
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DSLAM d50
Abstract: H10S-11 RxSD24
Text: Advance Information MC92460EC/D Rev. 1.0, 7/2002 MC92460 HDLC Controller Hardware Specifcations NCSD Applications This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MC92460 Multichannel HDLC
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MC92460EC/D
MC92460
MC92460IBIS
MC92460ZU
DSLAM d50
H10S-11
RxSD24
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PDF
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hdlc
Abstract: LC4256ZE 4000ZE CRC-16 CRC-32 VHDL CODE FOR HDLC controller ispLEVER iso
Text: HDLC Controller Implemented in ispMACH 4000ZE and CPLD Families July 2009 Reference Design RD1009 Introduction High-Level Data Link Control HDLC is published by the International Standards Organization (ISO). This data link protocol is located at the link layer (layer 2) of the 7-layer OSI reference model. Today, a variety of link layer protocols such as LAPB, LAPD, LLC and SDLC are based on the HDLC protocol with a few modifications. These singlechannel and multi-channel HDLC controller reference designs, targeted for the ispMACH 4000ZE, 4000 and
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4000ZE
RD1009
4000ZE,
5000VG
LC4256ZE-7MN144C,
1-800-LATTICE
hdlc
LC4256ZE
CRC-16
CRC-32
VHDL CODE FOR HDLC controller
ispLEVER iso
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fireberd
Abstract: design of HDLC controller using vhdl TTC fireberd 6000A
Text: MC-XIL-HDLC Single-Channel HDLC Controller April 15, 2003 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation User Guide, Data Sheet Design File Formats VHDL, Verilog source RTL1 Constraints File .ucf Verification
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TFC 718 S
Abstract: AR12-B5 AR11 AR13 T7121 T7121-EL T7121-EL2 T7121-PL T7121-PL2 T7250C
Text: Data Sheet April 1997 T7121 HDLC Interface for ISDN HIFI-64 Features • Low-cost device for B-channel (64 kbits/s) or D-channel (16 kbits/s) data transport. ■ Optional transparent mode—no HDLC framing is performed. ■ Frame sync (FS) allows a slot-select feature to
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T7121
HIFI-64)
T7250C.
DS96-357ISDN
DS90-087SMOS,
AY95-006ISDN,
TN96-010ISDN)
TFC 718 S
AR12-B5
AR11
AR13
T7121-EL
T7121-EL2
T7121-PL
T7121-PL2
T7250C
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