A54SX32A
Abstract: A54SX72A PAR64 REQ64 RT54SX-S CQFP 208 PIN
Text: v2.0 HiRel SX-A Family FPGAs Features and Benefits • Leading Edge Performance • • • • • • • • • • • 215 MHz System Performance Military Temperature 5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature) 240 MHz Internal Performance (Military Temperature)
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A54SX72
Abstract: actel cqfp 84
Text: Advanced v1.1 HiRel SX-A Family FPGAs Le a di n g E d ge P er f o r m a n ce • Cold-Sparing Capability • 215 MHz System Performance Military Temperature • Slow Slew Rate Option • 5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature) • QML Certified Devices
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A54SX32A
Abstract: A54SX72A PAR64 REQ64 RT54SX-S
Text: Advanced v1.2 HiRel SX-A Family FPGAs L ea d i n g E dg e P e rf o rm an c e • Cold-Sparing Capability • 215 MHz System Performance Military Temperature • Slow Slew Rate Option • 5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature) • QML Certified Devices
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54SX32
Abstract: A54SX32 A54SX32A A54SX72A PAR64 REQ64 54SX32A il 074
Text: Preliminary v1.0 HiRel SX-A Family FPGAs Le a di n g E d ge P er f o r m a n ce • QML Certified Devices • 215 MHz System Performance Military Temperature • 100% Military Temperature Tested (–55°C and +125°C) • 5.3ns Clock-to-Out (Pin-to-Pin) (Military Temperature)
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54SX32
Abstract: 54SX32A SX FPGAs A54SX32 A54SX32A A54SX72A PAR64 REQ64
Text: Preliminary v1.0 HiRel SX-A Family FPGAs Le a di n g E d ge P er f o r m a n ce • QML Certified Devices • 215 MHz System Performance Military Temperature • 100% Military Temperature Tested (–55°C and +125°C) • 5.3ns Clock-to-Out (Pin-to-Pin) (Military Temperature)
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diode 2U 66
Abstract: No abstract text available
Text: v5.1 SX-A Family FPGAs Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops
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Untitled
Abstract: No abstract text available
Text: v2.1 SX-A Automotive Family FPGAs Specifications • 12,000 to 108,000 Available System Gates • Up to 360 User-Programmable I/O Pins • Up to 2,012 Dedicated Flip-Flops • 0.22µ CMOS Process Technology Features u e • Nonvolatile • Configurable I/O Support for 3.3V PCI, 3.3V LVTTL,
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A54SX16A
Abstract: No abstract text available
Text: v2.0 SX-A Automotive Family FPGAs Specifications • 12,000 to 108,000 Available System Gates • Up to 360 User-Programmable I/O Pins • Up to 2,012 Dedicated Flip-Flops • 0.22µ CMOS Process Technology Features u e • Nonvolatile • Configurable I/O Support for 3.3V PCI, 3.3V LVTTL,
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22B2 DIODE
Abstract: A54SX08A A54SX16A A54SX32A A54SX72A PQ208 TQ100 TQ144 TQ176
Text: v5.2 SX-A Family FPGAs u e Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops
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22B2 DIODE
Abstract: RTSX-S datasheet SX FPGAs A54SX08A A54SX16A A54SX32A A54SX72A PQ208 TQ100 TQ144
Text: v5.1 SX-A Family FPGAs Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops
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A54SX72A
Abstract: A54SX08A A54SX16A A54SX32A RT54SX72S RT54SX-S
Text: v2.2 SX-A Automotive Family FPGAs Specifications • 12,000 to 108,000 Available System Gates • Up to 360 User-Programmable I/O Pins • Up to 2,012 Dedicated Flip-Flops • 0.22µ CMOS Process Technology Features u e • Nonvolatile • Configurable I/O Support for 3.3V PCI, 3.3V LVTTL,
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ACTEL FBGA 144
Abstract: A54SX16A
Text: v2.0 SX-A Automotive Family FPGAs Specifications • 12,000 to 108,000 Available System Gates • Up to 360 User-Programmable I/O Pins • Up to 2,012 Dedicated Flip-Flops • 0.22µ CMOS Process Technology Features u e • Nonvolatile • Configurable I/O Support for 3.3V PCI, 3.3V LVTTL,
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tms 980 can bus automotive
Abstract: ProASIC PLUS
Text: v2.0 SX-A Automotive Family FPGAs Specifications • 12,000 to 108,000 Available System Gates • Up to 360 User-Programmable I/O Pins • Up to 2,012 Dedicated Flip-Flops • 0.22µ CMOS Process Technology Features u e • Nonvolatile • Configurable I/O Support for 3.3V PCI, 3.3V LVTTL,
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sx08a
Abstract: No abstract text available
Text: v4.0 SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades
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22B2 DIODE
Abstract: Theta JC of FBGA A54SX08A A54SX16A A54SX32A A54SX72A PQ208 TQ100 TQ144 TQ176
Text: v5.3 SX-A Family FPGAs u e Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops
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A54SX72
Abstract: No abstract text available
Text: Advanced v.1 HiRel SX-A Family FPGAs Le a di n g E d ge P er f o r m a n ce • 100% Military Temperature Tested –55°C to +125°C • 215 MHz System Performance (Military Temperature) • 66 MHz PCI Compliant • 5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature)
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A54SX72* radiation
Abstract: cg624 A54SX72A actel 1020 datasheet RT54SX72S RT54SX-S TM1019 HiRel a54sx72a unused
Text: Advanced v1.4 RT54SX-S RadTolerant FPGAs for Space Applications S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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RT54SX-S
TM1019
A54SX72* radiation
cg624
A54SX72A
actel 1020 datasheet
RT54SX72S
RT54SX-S
HiRel a54sx72a unused
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HiRel a54sx72a unused
Abstract: No abstract text available
Text: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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RT54SX-S
RT54SX-S
TM1019
HiRel a54sx72a unused
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HiRel a54sx72a unused
Abstract: No abstract text available
Text: Advanced v1.6 RTSX-S RadTolerant FPGAs for Space Application S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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TM1019
HiRel a54sx72a unused
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HiRel a54sx72a unused
Abstract: No abstract text available
Text: Advanced v1.5 RTSX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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TM1019
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