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    HSTL STANDARDS Search Results

    HSTL STANDARDS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    DE6B3KJ151KA4BE01J Murata Manufacturing Co Ltd Safety Standard Certified Lead Type Disc Ceramic Capacitors for Automotive Visit Murata Manufacturing Co Ltd
    DE6B3KJ471KB4BE01J Murata Manufacturing Co Ltd Safety Standard Certified Lead Type Disc Ceramic Capacitors for Automotive Visit Murata Manufacturing Co Ltd
    DE6E3KJ152MN4A Murata Manufacturing Co Ltd Safety Standard Certified Lead Type Disc Ceramic Capacitors for Automotive Visit Murata Manufacturing Co Ltd
    DE6B3KJ101KA4BE01J Murata Manufacturing Co Ltd Safety Standard Certified Lead Type Disc Ceramic Capacitors for Automotive Visit Murata Manufacturing Co Ltd
    DE6B3KJ331KB4BE01J Murata Manufacturing Co Ltd Safety Standard Certified Lead Type Disc Ceramic Capacitors for Automotive Visit Murata Manufacturing Co Ltd

    HSTL STANDARDS Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    JESD86

    Abstract: JESD8-6 HSTL standards MAX9310 MAX9311 MAX9312 MAX9313 MAX9314 MAX9315 MAX9316
    Text: Maxim > App Notes > COMMUNICATIONS CIRCUITS Keywords: HSTL, PECL, high speed, interface standards, differential HSTL, high speed transceiver logic, Jedec standard, Jedec std, differential Sep 27, 2002 APPLICATION NOTE 1752 Applying HSTL Signals to PECL Input Devices


    Original     		PDF MAX9312: MAX9313: MAX9314: MAX9315: MAX9316: MAX9317: MAX9320: MAX9321: MAX9322: MAX9325: JESD86 JESD8-6 HSTL standards MAX9310 MAX9311 MAX9312 MAX9313 MAX9314 MAX9315 MAX9316

    8T33FS6221

    Abstract: No abstract text available
    Text: DATA SHEET MC100ES6221 Freescale Semiconductor Technical Data Rev 5, 04/2005 Low Voltage 1:20 Differential ECL/PECL/HSTL Clock LowBuffer Voltage 1:20 Differential Fanout MC100ES6221 MC100ES6221 ECL/PECL/HSTL Clock Buffer PRODUCT DISCONTINUATION NOTICEFanout


    Original     		PDF MC100ES6221 MC100ES6221 199707558G 8T33FS6221

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET MC100ES6221 Freescale Semiconductor Technical Data Rev 5, 04/2005 Low Voltage 1:20 Differential ECL/PECL/HSTL Clock LowBuffer Voltage 1:20 Differential Fanout ECL/PECL/HSTL Clock Fanout Buffer The MC100ES6221 is a bipolar monolithic differential clock fanout buffer.


    Original     		PDF MC100ES6221 MC100ES6221 199707558G

    AN1545

    Abstract: MC100EP221 MC100ES6221
    Text: DATA SHEET MC100ES6221 Freescale Semiconductor Technical Data Rev 5, 04/2005 Low Voltage 1:20 Differential ECL/PECL/HSTL Clock LowBuffer Voltage 1:20 Differential Fanout ECL/PECL/HSTL Clock Fanout Buffer The MC100ES6221 is a bipolar monolithic differential clock fanout buffer.


    Original     		PDF MC100ES6221 MC100ES6221 199707558G AN1545 MC100EP221

    HSTL standards

    Abstract: JESD8-6 JESD86 XAPP133 HSTL class I
    Text: Tech Topics High-Speed Transceiver Logic HSTL Introduction Virtex Series of FPGAs feature the Xilinx exclusive SelectI/O+ technology integrating support for 20 single-ended and differential I/O standards. HSTL is one of the single-ended I/O interfaces supported by every Virtex device, eliminating the need for external level translators


    Original     		PDF XAPP133: com/xapp/xapp133 HSTL standards JESD8-6 JESD86 XAPP133 HSTL class I

    Untitled

    Abstract: No abstract text available
    Text: CDCLVP110 www.ti.com SCAS683D – JUNE 2002 – REVISED JANUARY 2011 Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver Check for Samples: CDCLVP110 FEATURES 1 • • • • • • • • • Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Differential LVPECL Clock


    Original     		PDF CDCLVP110 SCAS683D 32-Pin MC100 EP111, ES6111, LVEP111, PTN1111

    Untitled

    Abstract: No abstract text available
    Text: JESD204B Clock Generator with 14 LVDS/HSTL Outputs AD9528 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS High performance wireless transceivers LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation


    Original     		PDF JESD204B AD9528 JESD204B OUT13/ OUT13 CP-72-6) AD9528BCPZ AD9528BCPZ-REEL7

    Untitled

    Abstract: No abstract text available
    Text: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SuperLite SY55857L FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle


    Original     		PDF 200ps 400ps 46mW/channel 10-pin SY55857L SY55857L

    857L

    Abstract: SY55857L SY55857LKI SY55857LKITR
    Text: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR DESCRIPTION FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle


    Original     		PDF 200ps 400ps 46mW/channel 10-pin SY55857L SY55857 SY55857L K10-1) 857L SY55857LKI SY55857LKITR

    SY55857L

    Abstract: SY55857UKI SY55857UKITR
    Text: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR DESCRIPTION FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle


    Original     		PDF 200ps 400ps 46mW/channel 10-pin SY55857L Translation00 SY55857 SY55857L K10-1) SY55857UKI SY55857UKITR

    Untitled

    Abstract: No abstract text available
    Text: Micrel, Inc. SuperLite SY55857L SuperLite™ 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SY55857L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature:


    Original     		PDF SY55857L SY55857L 200ps 400ps 46mW/channel 10-pin M9999-070605

    857l

    Abstract: SY55857L SY55857LKG SY55857LKGTR SY55857LKI SY55857LKITR SY58021U
    Text: Micrel, Inc. SuperLite SY55857L SuperLite™ 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SY55857L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature:


    Original     		PDF SY55857L 200ps 400ps 46mW/channel 10-pin SY55857L M9999-082306 857l SY55857LKG SY55857LKGTR SY55857LKI SY55857LKITR SY58021U

    857L

    Abstract: No abstract text available
    Text: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SuperLite SY55857L FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle


    Original     		PDF SY55857L 200ps 400ps 46mW/channel 10-pin SY55857L 857L

    857l

    Abstract: 10-PIN SY55857L SY55857LKG SY55857LKGTR SY55857LKI SY55857LKITR
    Text: Micrel, Inc. SuperLite SY55857L SuperLite™ 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SY55857L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature:


    Original     		PDF SY55857L 200ps 400ps 46mW/channel 10-pin SY55857L M9999-102605 857l 10-PIN SY55857LKG SY55857LKGTR SY55857LKI SY55857LKITR

    Untitled

    Abstract: No abstract text available
    Text: JESD204B Clock Generator with 14 LVDS/HSTL Outputs AD9528 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS High performance wireless transceivers LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation


    Original     		PDF JESD204B AD9528 JESD204B OUT13/ OUT13 CP-72-6) AD9528BCPZ AD9528BCPZ-REEL7

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Preliminary Information Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer The Motorola MC100ES6221 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems,


    Original     		PDF MC100ES6221/D MC100ES6221 MC100ES6221 JESD51-6 JES51-6

    Untitled

    Abstract: No abstract text available
    Text: 3.3V 2.5Gbps ANY INPUT-to-LVPECL DIFFERENTIAL TRANSLATOR Micrel, Inc. Precision Edge ® SY89327L Precision Edge SY89327L FEATURES Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML Guaranteed AC performance over temp and voltage:


    Original     		PDF SY89327L 400ps 200ps SY89327L M9999-071707

    SPARTAN XC2S50

    Abstract: SPARTAN-II SPARTAN-II xc2s100 pq208 CS144 FG256 PQ208 TQ144 VQ100 XC2S100 XC2S15
    Text: Robust Feature Set • Flexible on-chip memory Distributed and Block Memory • 4 Digital Delay Lock Loops per device Efficient chip level/ board level clock management • Select I/O Technology Interface to all major bus standards HSTL, GTL, SSTL, etc…


    Original     		PDF PQ208 FG256 FG456 SPARTAN XC2S50 SPARTAN-II SPARTAN-II xc2s100 pq208 CS144 FG256 PQ208 TQ144 VQ100 XC2S100 XC2S15

    857L

    Abstract: No abstract text available
    Text: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SuperLite SY55857L FINAL FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle


    Original     		PDF 200ps 400ps 46mW/channel 10-pin SY55857L 857L

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA Freescale Semiconductor, Inc. Order Number: MC100ES6221/D SEMICONDUCTOR TECHNICAL DATA Freescale Semiconductor, Inc. Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer The Motorola MC100ES6221 is a bipolar monolithic differential clock


    Original     		PDF MC100ES6221/D MC100ES6221 MC100ES6221 JES51-7 JESD51-3

    SY89327LMGTR

    Abstract: SY55857L SY89327L SY89327LMITR
    Text: Precision Edge ® SY89327L Precision Edge 3.3V 2.5Gbps ANY INPUT-to-LVPECL DIFFERENTIAL TRANSLATOR Micrel, Inc. SY89327L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC performance over temp and voltage:


    Original     		PDF SY89327L 400ps 200ps 10psPP M9999-071707 SY89327LMGTR SY55857L SY89327L SY89327LMITR

    SY55857L

    Abstract: SY89325LMGTR SY89327L SY89327LMITR sstl lvttl Translator microleadframe
    Text: Precision Edge ® SY89327L Precision Edge 3.3V 2.5Gbps ANY INPUT-to-LVPECL DIFFERENTIAL TRANSLATOR Micrel, Inc. SY89327L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC performance over temp and voltage:


    Original     		PDF SY89327L 400ps 200ps 10psPP M9999-072005 SY55857L SY89325LMGTR SY89327L SY89327LMITR sstl lvttl Translator microleadframe

    SY55857L

    Abstract: SY89327L SY89327LMITR
    Text: Precision Edge 3.3V 2.5Gbps ANY INPUT-to-LVPECL DIFFERENTIAL TRANSLATOR Micrel SY89327L Precision Edge™ SY89327L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC performance over temp and voltage:


    Original     		PDF SY89327L 400ps 200ps 10psp-p M9999-042704 SY55857L SY89327L SY89327LMITR

    QSP24F

    Abstract: No abstract text available
    Text: For technical assistance call the Microelectronics Products number on the back cover. PO U H N S General Information The HSTL Dual Terminator is designed pri­ marily for terminating bus lines in HSTL systems High-Speed-Transceiver-Logic . Resistor values have been selected so


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