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    irf -100v/10a

    Abstract: 25TTS IR185BG08DCB
    Text: Bulletin I0209J rev. A 09/99 IR185BG08DCB PHASE CONTROL THYRISTORS Junction Size: Square 185 mils Wafer Size: 4" VRRM Class: 800 V Passivation Process: Glassivated MESA Reference IR Packaged Part: 25TTS Series Major Ratings and Characteristics Parameters Units


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    PDF I0209J IR185BG08DCB 25TTS irf -100v/10a IR185BG08DCB

    XO2-640

    Abstract: "lattice semiconductor" sigma Delta MACHXO2
    Text: T H E D O - I T - A L L P L D The MachXO2 family of non-volatile infinitely reconfigurable Programmable Logic Devices PLDs is designed for system applications found in telecommunications infrastructure, computing, industrial and medical equipment. Combining an optimized lookup table (LUT) architecture with 65-nm embedded Flash


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    PDF 65-nm 1-800-LATTICE I0209 XO2-640 "lattice semiconductor" sigma Delta MACHXO2

    CABGA

    Abstract: sram 2112 jtag sequence lattice MachXO2 embedded application in medical field in TQFP 144 PACKAGE lattice Lattice XO2 spi lpc MACHXO2
    Text: D O - I T - A L L P L D Optimized for System Control Applications The MachXO2 family of non-volatile infinitely reconfigurable Programmable Logic Devices PLDs is designed for system control applications found in telecommunications infrastructure, computing, industrial


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    PDF 65-nm 1-800-LATTICE I0209 CABGA sram 2112 jtag sequence lattice MachXO2 embedded application in medical field in TQFP 144 PACKAGE lattice Lattice XO2 spi lpc MACHXO2

    jtag sequence lattice MachXO2

    Abstract: 65nm sram MACHXO2 XO2-7000
    Text: システム・アプリケーション用に最適化 不揮発性メモリを集積し何度でも再構成可能なPLD のMachXO2 ファミリは、通信インフラストラクチャ やコンピューティング、そして産業と医療機器のアプ


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    PDF MachXO23 240KbitsysMEMTM 54Kbit 256Kbit ASI56 20x20mm, 14x14mm, 17x17mm, 23x23mm, jtag sequence lattice MachXO2 65nm sram MACHXO2 XO2-7000

    jtag sequence lattice MachXO2

    Abstract: MACHXO2 Lattice XO2 spi lpc XO2-7000 lpc interface sram XO2-1200 XO2-4000 spi flash controller lattice 1024
    Text: 全 功 能 的 P L D 应 统化 系 用而优 为 专 MachXO2系列 专为系统应用而优化 MachXO2 系列非易失性无限可重构可编程逻辑器件 PLD 专为系统应用而设计,适用于电信基础设施计 算、工业和医疗设备。结合优化的查找表 (LUT) 结构和


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    PDF 65MachXO2 335I/O 20x20mm, 14x14mm, 17x17mm, 23x23mm, Corporation2010 I0209C jtag sequence lattice MachXO2 MACHXO2 Lattice XO2 spi lpc XO2-7000 lpc interface sram XO2-1200 XO2-4000 spi flash controller lattice 1024

    Untitled

    Abstract: No abstract text available
    Text: M29W004T M29W004B 4 Mbit 512Kb x8, Block Erase Low Voltage Single Supply Flash Memory • 2.7V to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ■ FAST ACCESS TIME: 100ns ■ FAST PROGRAMMING TIME: 1Ojas typical ■ PROGRAM/ERASE CONTROLLER (P/E.C.)


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    PDF M29W004T M29W004B 512Kb 100ns M29W004T,

    d3250

    Abstract: SN64BCT245
    Text: SN64BCT245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS040— I0209D3250, JA N U A R Y 1990 BiCMOS Design Substantially Reduces Standby Current DW OR N PACKAGE • High-lmpedance State During Power Up and Power Down • ESD Protection Exceeds 2000 V per


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    PDF SN64BCT245 SCBS040â TI0209â D3250, MIL-STD-883C 300-mil d3250 SN64BCT245

    L0438

    Abstract: l0433
    Text: Low Mating Force input/output connector «- • # A - '— r -c l “'' _-IIL—/_ !_ : KC .r\ .4 4 5 M A X UNM ATED FREE LENGTH LOCKING SCREW 1 0 -5 0 2 5 9 9 -2


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