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    I860 64-BIT MICROPROCESSOR PERFORMANCE BRIEF Search Results

    I860 64-BIT MICROPROCESSOR PERFORMANCE BRIEF Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TMP89FS60AUG Toshiba Electronic Devices & Storage Corporation 8-bit Microcontroller/Processing Performance Equivalent to a 16-bit MCU/LQFP64-P-1010-0.50E Visit Toshiba Electronic Devices & Storage Corporation
    TMP89FS63AUG Toshiba Electronic Devices & Storage Corporation 8-bit Microcontroller/Processing Performance Equivalent to a 16-bit MCU/LQFP52-P-1010-0.65 Visit Toshiba Electronic Devices & Storage Corporation
    TMP89FS60BFG Toshiba Electronic Devices & Storage Corporation 8-bit Microcontroller/Processing Performance Equivalent to a 16-bit MCU/P-LQFP64-1414-0.80-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMP89FS63BUG Toshiba Electronic Devices & Storage Corporation 8-bit Microcontroller/Processing Performance Equivalent to a 16-bit MCU/P-LQFP52-1010-0.65-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMP89FS62AUG Toshiba Electronic Devices & Storage Corporation 8-bit Microcontroller/Processing Performance Equivalent to a 16-bit MCU/LQFP44-P-1010-0.80A Visit Toshiba Electronic Devices & Storage Corporation

    I860 64-BIT MICROPROCESSOR PERFORMANCE BRIEF Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    512Kx32x4

    Abstract: vhdl GPCM TADM042G5 block diagram 8085 microprocessor based traffic control system
    Text: Preliminary Data Sheet November 2001 Quad-Port Gigabit Ethernet Over SONET/SDH Smart Silicon Solution Features Overview • Encapsulates GbE frames into the SONET/SDH protocol using packet-over-SONET POS format. ■ Support for jumbo Ethernet packets (9.6 kbytes in


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    PDF DS02-055NCIP DS01-230NCIP) 512Kx32x4 vhdl GPCM TADM042G5 block diagram 8085 microprocessor based traffic control system

    award BIOS 32 Pin PLCC

    Abstract: BIOS 32 Pin PLCC Phoenix Bios IC pin Number laptop motherboard schematic laptop motherboard resistors microprocessor 80286 internal architecture Phoenix BIOS 32 Pin PLCC laptop MOTHERBOARD Chip Level MANUAL ic laptop motherboard ami BIOS 32 Pin PLCC
    Text: AP-341 APPLICATION NOTE Designing an Updatable BIOS Using FLASH Memory BRIAN DIPERT DON VERNER MCD MARKETING APPLICATIONS December 1995 Order Number 292077-005 Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in


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    PDF AP-341 28F001BX-T 28F001BX-B award BIOS 32 Pin PLCC BIOS 32 Pin PLCC Phoenix Bios IC pin Number laptop motherboard schematic laptop motherboard resistors microprocessor 80286 internal architecture Phoenix BIOS 32 Pin PLCC laptop MOTHERBOARD Chip Level MANUAL ic laptop motherboard ami BIOS 32 Pin PLCC

    VT138

    Abstract: ASA17
    Text: XRT86SH221 PRELIMINARY SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH SEPTEMBER 2006 REV. P1.0.1 GENERAL DESCRIPTION The XRT86SH221 Voyager-Lite is a physical layer SDH to PDH mapper/demapper which enables E1 aggregation to STM-1 via standard VC-12 to AU-3


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    PDF XRT86SH221 21-CHANNEL VC-12 VT138 ASA17

    user manual of XRT91L31

    Abstract: No abstract text available
    Text: XRT86SH328 SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC MAY 2008 REV. 1.0.0 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/ STM0 via standard VT1.5/VT2 or VC-11/VC-12 to


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    PDF XRT86SH328 28-T1/21-E1 VC-11/VC-12 user manual of XRT91L31

    G706

    Abstract: truth table varification
    Text: XRT86SH328 PRELIMINARY SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC SEPTEMBER 2007 REV. P1.0.1 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/


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    PDF XRT86SH328 28-T1/21-E1 VC-11/VC-12 G706 truth table varification

    traffic light using 68K

    Abstract: MCP860 AU-AIS alarm
    Text: XRT86SH328 PRELIMINARY SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC SEPTEMBER 2007 REV. P1.0.0 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/


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    PDF XRT86SH328 28-T1/21-E1 VC-11/VC-12 traffic light using 68K MCP860 AU-AIS alarm

    Untitled

    Abstract: No abstract text available
    Text: XRT86SH328 PRELIMINARY SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC NOVEMBER 2007 REV. P1.0.2 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/


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    PDF XRT86SH328 28-T1/21-E1 VC-11/VC-12

    XRT91L31

    Abstract: No abstract text available
    Text: XRT86SH328 SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC JUNE 2010 REV. 2.0.0 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/ STM0 via standard VT1.5/VT2 or VC-11/VC-12 to


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    PDF XRT86SH328 28-T1/21-E1 VC-11/VC-12 XRT91L31

    intel i860

    Abstract: A80860XR-40 pbit 2180 a80860xr-33 A80860XR40 TE 2197 transistor 8550 sad intel I860 processor pin diagram of XR 2206 i860 64-Bit Microprocessor Performance Brief
    Text: i860 XR 64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock ' — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock ■ High Performance Design — 25/33.3/40 MHz Clock Rates


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    PDF 64-BIT 128-Bit 32-Bit 32/64-Bit intel i860 A80860XR-40 pbit 2180 a80860xr-33 A80860XR40 TE 2197 transistor 8550 sad intel I860 processor pin diagram of XR 2206 i860 64-Bit Microprocessor Performance Brief

    Untitled

    Abstract: No abstract text available
    Text: i860 XR 64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock ■ High Performance Design — 25/33.3/40 MHz Clock Rates


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    PDF 64-BIT 128-Bit 32-Bit 32/64-Bit

    00A75

    Abstract: INTEL Core i7 860 J 80222 lm 6358 J1 3009-2 271121 Texture mapping CC1105 Intel i860
    Text: P K H IL D fiflD M M V MILITARY i860 XR 32/64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock ■ High Performance Design


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    PDF i860TM 32/64-BIT 64-Bit 128-Bit 32-Bit CG/SALE/101789 00A75 INTEL Core i7 860 J 80222 lm 6358 J1 3009-2 271121 Texture mapping CC1105 Intel i860

    Untitled

    Abstract: No abstract text available
    Text: in te * MILITARY i860 64-BIT MICROPROCESSOR Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock • Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for


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    PDF 64-BIT /i486TM

    Untitled

    Abstract: No abstract text available
    Text: i860 64-BIT MICROPROCESSOR • Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for Binary Floating-Point Arithmetic — 386™ /i486TM Microprocessor Data Formats and Page Table Entries — JEDEC 168-pin Ceramic Pin Grid Array Package see Packaging


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    PDF 64-BIT /i486TM 168-pin 128-Bit

    FGT 313

    Abstract: N06010 a3058c 271121 intel i860
    Text: [ p fô iy iiM A O W in te L MILITARY i860 XR 32/64-BIT MICROPROCESSOR Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Tw o Floating-Point Results per Clock High Perform ance Design


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    PDF 64-Bit 128-Bit 32/64-B i860TM 32/64-BIT CG/SALE/101789 FGT 313 N06010 a3058c 271121 intel i860

    ba 6414 fs

    Abstract: RTL 2832 A80860XP i860Xp 80860XR 80860XP equivalent of transistor tt 2148 transistor x 313 ca 361 e ic 82490XP
    Text: intei I860 XP MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction — Up to Two Floating-Point Results ■ High Performance Design — 40/50 MHz Clock Rate — 100 Peak Single Precision MFLOPS


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    PDF I860TM 64-Bit 128-Bit 32-Bit 32/64-Bit ba 6414 fs RTL 2832 A80860XP i860Xp 80860XR 80860XP equivalent of transistor tt 2148 transistor x 313 ca 361 e ic 82490XP

    FGT 313

    Abstract: No abstract text available
    Text: in te i ¡860 XR 64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for


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    PDF 64-BIT lntel386TM/486TM 168-pin 128-Bit 80860XR FGT 313

    Intel i860

    Abstract: No abstract text available
    Text: INTEL CORP UP/PRPHLS bflE » • 4ñ2bl7S Dia^flSb in te i i860 XR 64-BIT MICROPROCESSOR ■ Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per


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    PDF 64-BIT 128-Bit 32-Bit 32/64-Bit 80860XR Intel i860

    led 7 segment LDS 5161 AK

    Abstract: led 7 segment LDS 5161 AH 7-segment 4 digit LFD 5522 AKO 701 434 tdso 5160 k lds 7 segment LDS 5161 AK led 7 segment LDS 5161 As manual LG VARIABLE FREQUENCY DRIVE is3 -20/led 7 segment LDS 5161 AH ako 544 126
    Text: NAM E; C O M P A N Y :. ADDRESS; . . C IT Y ; S TA TE: Z IP : C O U N T R Y :. P H O N E N O .; . .I — ;.-,. ' - V- ORDER NO. QTY. TITLE fTTT ±j . • . n i i lU . . II 11 1 i i 1111 1-T 2 .-.


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    PDF X011-6 178Erasm X011-2712-803-8294 12thFloor, 15thFloor, 18479R X23756S led 7 segment LDS 5161 AK led 7 segment LDS 5161 AH 7-segment 4 digit LFD 5522 AKO 701 434 tdso 5160 k lds 7 segment LDS 5161 AK led 7 segment LDS 5161 As manual LG VARIABLE FREQUENCY DRIVE is3 -20/led 7 segment LDS 5161 AH ako 544 126

    Untitled

    Abstract: No abstract text available
    Text: [P K IILO fiilD M A lS V in te i 82495XP CACHE CONTROLLER/ 82490XP CACHE RAM MESI Cache Consistency Protocol Hardware Cache Snooping Maintains Consistency with Primary Cache via Inclusion Principle Flexible User-Implemented Memory Interface Enables Wide Range of


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    PDF 82495XP 82490XP 208-Lead 84Lead

    xxxjx

    Abstract: No abstract text available
    Text: in t e i 82495XP CACHE CONTROLLER/ 82490XP CACHE RAM Two-Way, Set Associative, Secondary Cache for i860 xp Microprocessor 50 MHz “No Glue” Interface with CPU Configurable — Cache Size 256 or 512 Kbytes — Line Width 32, 64 or 128 Bytes — Memory Bus Width 64 or 128 Bits


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    PDF 82495XP 82490XP 10-3a. Controiler/82490XP xxxjx

    MTA02

    Abstract: i860Xp MT 8222 Intel 82495 Cache Controller 3ce-14 LR1 D09 ahy 103 i860 64-Bit Microprocessor Performance Brief MCache Second Level Cache-Controller
    Text: in t e ! 82495XP CACHE CONTROLLER/ 82490XP CACHE RAM Two-Way, Set Associative, Secondary Cache for i860 XP Microprocessor 50 MHz “No Glue” Interface with CPU Configurable — Cache Size 256 or 512 Kbytes — Line Width 32, 64 or 128 Bytes — Memory Bus Width 64 or 128 Bits


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    PDF 82495XP 82490XP Controller/82490XP MTA02 i860Xp MT 8222 Intel 82495 Cache Controller 3ce-14 LR1 D09 ahy 103 i860 64-Bit Microprocessor Performance Brief MCache Second Level Cache-Controller

    est 7502 b data sheet

    Abstract: No abstract text available
    Text: P E H I1 0 IM 1 D B M IV i n Dt t e : s. i 991 82495XP CACHE CONTROLLER/ 82490XP CACHE RAM • Two-Way, Set Associative, Secondary Cache for i860 XP Microprocessor MESI Cache Consistency Protocol ■ 50 MHz “No Glue” Interface with CPU Maintains Consistency with Primary


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    PDF 82495XP 82490XP 10-3a. Controller/82490XP est 7502 b data sheet

    85C508

    Abstract: Intel 85C508 290175 incir
    Text: i n t o l. 85C508 FAST 1-MICRON CHMOS DECODER/LATCH juPLD • High-Performance Programmable Logic Device for High-Speed Microprocessorto-Memory Decode ■ 16 Dedicated Inputs for Address/Data Bus Decoding; 8 Latched Outputs; 1 Global Latch Enable ■ Supports Intel386 , i468TM, ¡860tm,


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    PDF 85C508 Intel386TM, i468TM, 860tm, 28-Pin 300-mil 85C508-7. 8SC508 Intel 85C508 290175 incir

    Untitled

    Abstract: No abstract text available
    Text: Intel INTEL486 FAMILY OF MICROPROCESSORS LOW POWER VERSION DATABOOK Low Power Intel486™ SX CPU/lntel487TM SX MCP Low Power Intel486 DX CPU Low er Power Dissipation — Dynamic Frequency Scalability — Icc m ax Reduced to 150 mA at 2 M Hz — Im proved V c c Rating ( ± 10% )


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    PDF INTEL486â CPU/lntel487TM Intel486 INTEL487â Intel487 169-pin