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Catalog Datasheet	MFG & Type	Document Tags	PDF
ICS-9LRS954A4GLF Abstract: ICS9LRS954A4GLF ICS9LPRS552AGLF ICS951417 ICS9LPRS587EGLF ICS951461BGLF ICS9LPRS365BGLF ICS9LPR363DGLF ICS954310 ICS9LPRS355BGLF Text: Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 96138 PCN #: A0807-02R1 Product Affected: PRODUCT/PROCESS CHANGE NOTICE PCN DATE: January 9, 2009 300 mil SSOP 48, 56 150 mil SOIC 8, 14, 16 300 mil SOIC 16, 18, 20, 24, 28, 32	Original	A0807-02R1 DESCRIPTION4LVC16827APAG IDT74LVC16827APAG8 IDT74LVCH16543APAG IDT74LVCH16543APAG8 IDT74LVCH16646APAG IDT74LVCH16646APAG8 IDT74LVCHR16646APAG IDT74LVCHR16646APAG8 IDTCV110NPAG ICS-9LRS954A4GLF ICS9LRS954A4GLF ICS9LPRS552AGLF ICS951417 ICS9LPRS587EGLF ICS951461BGLF ICS9LPRS365BGLF ICS9LPR363DGLF ICS954310 ICS9LPRS355BGLF	PDF
ICS93718 Abstract: ICS950901 SEL24 PC133 registered reference design VIA P4X266 ics93712 Text: ICS950901 Integrated Circuit Systems, Inc. Programmable Timing Control Hub for P4™ Recommended Application: VIA P4X266 chipset with PC133 or DDR memory. Pin Configuration 1 SEL24_48/REF VDDREF GND X1 X2 VDD48 FS3/48MHz FS2/24_48MHz GND FS0/PCICLK_F	Original	ICS950901 P4X266 PC133 48/REF VDD48 FS3/48MHz FS2/24 48MHz MO-118 ICS950901yFT ICS93718 ICS950901 SEL24 PC133 registered reference design VIA P4X266 ics93712	PDF
7400 series CMOS Logic ICs Abstract: VIA P4X266 ICS93712 ICS93718 ICS950905 SEL24 ICS93715 PC133 registered reference design 7400 fan-out Text: ICS950905 Advance Information Integrated Circuit Systems, Inc. Programmable Timing Control Hub for P4™ Output Features: • 2 - Pair of differential CPU clocks @ 3.3V • 1 - Pair of differential push pull CPU_CS clocks @ 2.5V • 3 - AGP @ 3.3V • 9 - PCI @ 3.3V	Original	ICS950905 48MHz 318MHz MO-118 ICS950904yFT 7400 series CMOS Logic ICs VIA P4X266 ICS93712 ICS93718 ICS950905 SEL24 ICS93715 PC133 registered reference design 7400 fan-out	PDF
ICS93718 Abstract: ICS950901 SEL24 P4X266 ICS93715 PC133 registered reference design Text: ICS950901 Integrated Circuit Systems, Inc. Programmable Timing Control Hub for P4™ Recommended Application: VIA P4X266 chipset with PC133 or DDR memory. Pin Configuration 1 SEL24_48/REF VDDREF GND X1 X2 VDD48 FS3/48MHz FS2/24_48MHz GND FS0/PCICLK_F	Original	ICS950901 P4X266 PC133 48/REF VDD48 FS3/48MHz FS2/24 48MHz ICS950901yFLFT ICS93718 ICS950901 SEL24 ICS93715 PC133 registered reference design	PDF