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    IEEE 32 BIT FLOATING POINT MULTIPLIER Search Results

    IEEE 32 BIT FLOATING POINT MULTIPLIER Result Highlights (5)

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    DFE2016CKA-1R0M=P2 Murata Manufacturing Co Ltd Fixed IND 1uH 1800mA NONAUTO Visit Murata Manufacturing Co Ltd
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    IEEE 32 BIT FLOATING POINT MULTIPLIER Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    DSP-3201

    Abstract: No abstract text available
    Text: ANALOG DEVICES 32-Bit IEEE Floating-Point Chipset ADSP-3201/ADSP-3202 FEATURES Complete Chipset Implementing Floating-Point Arithmetic Fully Compatible with IEEE Standard 754 Arithmetic Operations on Three Data Formats: 32-Bit Single-Precision Floating Point


    OCR Scan     		32-Bit ADSP-3211 ADSP-3221 240ns 750mW 144-Lead OOUT31 DSP-3201 PDF

    Untitled

    Abstract: No abstract text available
    Text: AN ALO G D E V IC E S □ IEEE Floating-Point DSP Microprocessor FEATU RES 20 MHz IEEE Floating-Point Processor IEEE 32-Bit Single-Precision and 40-Bit Extended Single-Precision Floating-Point Formats 32-Bit Fixed-Point Formats, Integer and Fractional Separate Program and Data Buses Extended Off-Chip


    OCR Scan     		32-Bit 40-Bit 32-Word, ADSP-21020 PDF

    ADSP-3201

    Abstract: ADSP3201
    Text: ANALOG DEVICES □ 32-Bit IEEE Floating-Point Chipset ADSP-3201/ADSP-3202 FEA T U R ES Complete Chipset Implementing Floating-Point Arithmetic Fully Compatible with IEEE Standard 754 Arithmetic Operations on Three Data Formats: 32-Bit Single-Precision Floating Point


    OCR Scan     		32-Bit ADSP-3201/ADSP-3202 ADSP-3211 ADSP-3221 240ns 750mW ADSP-3201 ADSP3201 PDF

    ADSP-3201

    Abstract: ADSP-3221 ADSP-1401 adsp3201 ADSP3202 ADSP-3202 ADSP-3128 ADSP3210 HB FULLER ADSP-3210
    Text: ANALOG DEVICES 32-Bit IEEE Floating-Point Chipset ADSP-3201/ADSP-3202 FEATURES Com plete Chipset Im plementing Floating-Point Arithm etic Fully Com patible w ith IEEE Standard 754 A rithm etic Operations on Three Data Formats: 32-Bit Single-Precision Floating Point


    OCR Scan     		32-Bit ADSP-3201/ADSP-3202 ADSP-3211 ADSP-3221 240ns 750mW ADSP-3201 ADSP-1401 adsp3201 ADSP3202 ADSP-3202 ADSP-3128 ADSP3210 HB FULLER ADSP-3210 PDF

    268-5400

    Abstract: weitek 268-5400-00 WTL1032 1u040 WTL1033 J1439
    Text: A- B, W OODARD & AS SO C INNOVATIONS IN MICROSYSTEM TECHNOLOGY WTL1032 WTL1033 4 0 8 7 3 3 -7 3 5 3 High-Speed 32-Bit IEEE Floating Point Multiplier High-Speed 32-Bit IEEE Floating Point ALU Features A complete floating-point arithmetic solution for high-speed processors


    OCR Scan     		WTL1032 32-Bit WTL1033 16-bit 100ns 200ns 900ns 1032JC/1033JC 268-5400 weitek 268-5400-00 1u040 J1439 PDF

    Untitled

    Abstract: No abstract text available
    Text: ANALOG DEVICES High Speed 64-Bit IEEE Floating-Point Multiplier _ ADSP-3210 1.1 Scope. This specification covers the detail requirements for a CMOS monolithic 32-bit and 64-bit IEEE Standard 754 format floating-point multiplier.


    OCR Scan     		64-Bit ADSP-3210 32-bit ADSP-3210SG/883B ADSP-3210TG/883B ADSP-3210UG/883B ADI-M-1000: G-100A. ADSP-3210 PDF

    ADSP-3210

    Abstract: ADSP3210 b 806
    Text: ANALOG DEVICES High Speed 64-Bit IEEE Floating-Point Multiplier _ ADSP-3210 1.1 Scope. This specification covers the detail requirements for a CMOS monolithic 32-bit and 64-bit IEEE Standard 754 format floating-point multiplier.


    OCR Scan     		64-Bit ADSP-3210 32-bit ADSP-3210SG/883B ADSP-3210TG/883B ADSP-3210UG/883B ADI-M-1000: G-100A. ADSP3210 b 806 PDF

    Untitled

    Abstract: No abstract text available
    Text: L64133 32-Bit HCMOS IEEE Floating-Point Processor Description LSI LOGIC The L64133 is a high-speed processor which contains a full 32-bit floating-point multiplier and a full 32-bit floating-point ALU on a single chip. This three-bus device has a clean archi­


    OCR Scan     		L64133 32-Bit P754-1985 144-pin PDF

    F2KV

    Abstract: No abstract text available
    Text: L64133 32-Bit HCMOS IEEE Floating-Point Processor LSI LOGIC Preliminary Description The L64133 is a high-speed processor which con­ tains a full 32-bit floating-point multiplier and a full 32-bit floating-point ALU on a single chip. This three-bus device has a clean architecture with no


    OCR Scan     		L64133 32-Bit L64133 P754-1985 144-pin 32-bitOffices F2KV PDF

    weitek

    Abstract: ncl051 WTL1165-060-GC 80386 microprocessor pin out diagram floating point handling LT 5251 1N3062 68-PIN WTL1163 1164-060
    Text: WTL 1164/WTL 1165 64-BIT IEEE FLOATING POINT MULTIPLIER/ DIVIDER AND ALU PRELIMINARY DATA Features A COMPLETE FLOATING POINT ARITHMETIC SOLUTION FOR HIGH-SPEED PROCESSORS AND COPROCESSORS FULL 32-BIT AND 64-BIT FLOATING POINT FORMAT AN D OPERATIONS, CONFORMING TO


    OCR Scan     		1164/WTL 64-BIT 32-BIT weitek ncl051 WTL1165-060-GC 80386 microprocessor pin out diagram floating point handling LT 5251 1N3062 68-PIN WTL1163 1164-060 PDF

    c3200 BL

    Abstract: TMC3200 nana j12 ir TMC3201 marking CYN C3200 equivalent TMC3200G5A
    Text: TRYw TMC3200, TMC3201 CM O S Floating-Point Arithmetic Unit and Multiplier 32/34 Bits The TMC3200, an arithmetic unit, adds and subtracts floating-point numbers expressed in IEEE 32-bit single­ precision format or extended-range 34-bit format. Conversions between floating-point and 24-bit two'scomplement integer fixed-point representations are


    OCR Scan     		TMC3200, TMC3201 32-bit 34-bit 24-bit TMC3201, TMC32Q0, TMC3200 TMC3201 c3200 BL nana j12 ir marking CYN C3200 equivalent TMC3200G5A PDF

    3222S

    Abstract: No abstract text available
    Text: ANALOG DEVICES □ FEATURES Complete 40 MFLOPS Floating-Point Chipset Multiplier/Divider and ALU Fully Compatible w ith IEEE Standard 754 Arithm etic Operations on Four Data Formats: 32-Bit Single-Precision Floating-Point 64-Bit Double-Precision Floating-Point


    OCR Scan     		64-Bit ADSP-3212/ADSP-3222 32-Bit 300ns 600ns 130ns 3222S PDF

    Untitled

    Abstract: No abstract text available
    Text: SHARC Embedded Processor ADSP-21261/ADSP-21262/ADSP-21266 SUMMARY Single-instruction multiple-data SIMD computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file


    Original     		ADSP-21261/ADSP-21262/ADSP-21266 32-bit floating-point/32-bit 40-bit BC-136 ST-144 PDF

    Untitled

    Abstract: No abstract text available
    Text: ANALOG DEVICES □ 64-Bit IEEE Floating-Point Chipset ADSP-3212/ADSP-3222 FEATURES Com plete 40 MFLOPS Floating-Point Chipset M ultiplier/D ivider and ALU Fully Com patible w ith IEEE Standard 754 A rithm etic Operations on Four Data Formats: 32-Bit Single-Precision Floating-Point


    OCR Scan     		64-Bit ADSP-3212/ADSP-3222 32-Bit 300ns 600ns 130ns PDF

    F2KV

    Abstract: 4x4 bit multipliers sulzer 8400 a11xx
    Text: L64133 32-Bit HCMOS IEEE Floating-Point Processor Preliminary Description T ST LOGIC •T T . V . X T WW M U f f S S The L64133 is a high-speed processor which con­ tains a full 32-bit floating-point multiplier and a full 32-bit floating-point ALU on a single chip. This


    OCR Scan     		L64133 32-Bit L64133 P754-1985 144-pin F2KV 4x4 bit multipliers sulzer 8400 a11xx PDF

    ADSP-21160

    Abstract: ADSP-21161 ADSP-21262 ADSP-21266 BLM18AG102SN1D 20BIT ADC
    Text: SHARC Embedded Processor ADSP-21262 a SUMMARY KEY FEATURES High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data SIMD computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/


    Original     		ADSP-21262 32-bit/40-bit 32-bit floating-point/32-bit 40-bit 136-Lead 144-Lead ADSP-21160 ADSP-21161 ADSP-21262 ADSP-21266 BLM18AG102SN1D 20BIT ADC PDF

    ADSP-21160

    Abstract: ADSP-21161 ADSP21261 ADSP-21261
    Text: SHARC Embedded Processor ADSP-21261 a SUMMARY KEY FEATURES High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data SIMD computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/


    Original     		ADSP-21261 32-bit/40-bit 32-bit floating-point/32-bit 40-bit ADSP-21261SKSTZ1502 ADSP-21261SKBCZ1502 D04932-0-3/06 136-Ball BC-136-3 ADSP-21160 ADSP-21161 ADSP21261 ADSP-21261 PDF

    spi flash parallel port

    Abstract: ADSP-21160 ADSP-21161 ADSP-21262 ADSP-21266 A2388
    Text: SHARC Embedded Processor ADSP-21262 a SUMMARY KEY FEATURES High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data SIMD computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/


    Original     		ADSP-21262 32-bit/40-bit 32-bit floating-point/32-bit 40-bit 136-Lead 144-Lead spi flash parallel port ADSP-21160 ADSP-21161 ADSP-21262 ADSP-21266 A2388 PDF

    m15m R2

    Abstract: ADSP-21XXX architecture ADSP-21020 adsp21020kg133
    Text: ANALOG ► DEVICES 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution


    OCR Scan     		1024-Point 32-Bit 40-Bit 80-Bit ADSP-21020KG-80 ADSP-21020KG-100 ADSP-21020KG-133 ADSP-21020BG-80 SP-21020BG-100 m15m R2 ADSP-21XXX architecture ADSP-21020 adsp21020kg133 PDF

    Untitled

    Abstract: No abstract text available
    Text: 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 ANALOG DEVICES FUNCTIONAL BLOCK DIAGRAM FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maxim izes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle


    OCR Scan     		32/40-Bit ADSP-21020 1024-Point 32-Bit 40-Bit 80-Bit 223-Lead PDF

    Untitled

    Abstract: No abstract text available
    Text: A. e PREHj INNOVATIONS IN MICROSYSTEM TECHNOLOGY WOODARD & ASSOC. ä\ T / ä 408 7 3 3 -7 3 5 3 WTL1032 High-Speed 32-Bit IEEE Floating Point Multiplier WTL1033 High-Speed 32-Bit IEEE Floating Point ALU Features A co m p lete flo atin g -p o in t a rith m etic solu tion


    OCR Scan     		WTL1032 32-Bit WTL1033 1032JC/1033JC 1032JM/1033JM 1032LC/1033LC 1032LM/1033LM PDF

    Untitled

    Abstract: No abstract text available
    Text: WTL 2264/WTL 2265 FLOATING POINT MULTIPLIER/ DIVIDER AND ALU PRELIMINARY DATA April 1986 Features HIGH SPEED CONFORMANCE TO IEEE STANDARD 754, VERSION 10.0 Full 32-bit and 64-bit floating point formats and opera­ tions 20 MFlops 50 ns pipelined for 32-bit ALU opera­


    OCR Scan     		2264/WTL 32-bit 64-bit 144-PIN PDF

    DSP-21020

    Abstract: DSP21020
    Text: NOV 3 m ANALOG ► DEVICES 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture M axim izes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle


    OCR Scan     		32/40-Bit ADSP-21020 1024-Point 32-Bit 40-Bit 80-Bit 223-Lead DSP-21020 DSP21020 PDF

    M 3211

    Abstract: Rapa SP-3211 SP3211
    Text: ANALOG DEVICES High Speed 64-Bit IEEE Floating-Point Multiplier ADSP-3211 1.1 Scope. This specification covers the detail requirements for a CMOS monolithic 32-bit and 64-bit IEEE Standard 754 format floating-point multiplier. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows:


    OCR Scan     		64-Bit ADSP-3211 32-bit ADSP-3211SG/883B ADSP-3211TG/883B ADSP-3211UG/883B ADI-M-1000: G-144A. SP-3211 M 3211 Rapa SP3211 PDF