PC 845 MOTHERBOARD CIRCUIT diagram
Abstract: PC 845 MOTHERBOARD VOLTAGE diagram inmos transputer T425 imsc004 ttm22 inmos transputer T225 PC 845 MOTHERBOARD CIRCUIT diagram PC KT805 IMSB426 inmos transputer reference manual
Text: TRANSPUTER TRAM SOLUTIONS Transtech Parallel Systems designs and manufactures embedded multi-processing products for OEM, end-user and scientific research applications. Transtech produces signal processing and computing systems based on SGSThomson transputers, PowerPC processors, Analog
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TMS320C4x
T8xC701
PC 845 MOTHERBOARD CIRCUIT diagram
PC 845 MOTHERBOARD VOLTAGE diagram
inmos transputer T425
imsc004
ttm22
inmos transputer T225
PC 845 MOTHERBOARD CIRCUIT diagram PC
KT805
IMSB426
inmos transputer reference manual
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MB86933H
Abstract: MB86930 MB86931 instruction set Sun SPARC T8 ADR27
Text: MB86933H 930 Series 32–BIT RISC EMBEDDED PROCESSOR November 1996 ADVANCE INFORMATION FEATURES • 25 MHz 40ns/cycle operating frequency • SPARC V8 high–performance RISC architecture • 1 KByte, direct mapped instruction cache • Flexible locking mechanism for instruction cache
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MB86933H
40ns/cycle)
MB86933H
MB86933.
MB86930
MB86931
instruction set Sun SPARC T8
ADR27
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instruction set Sun SPARC T3
Abstract: SPARC v8 architecture BLOCK DIAGRAM MB86930 MB86931 ADR27 MB86933H-25PF-G-B
Text: MB86933H 930 Series 32–BIT RISC EMBEDDED PROCESSOR SEPTEMBER 1996 ADVANCE INFORMATION FEATURES • 25 MHz 40ns/cycle operating frequency • SPARC V8 high–performance RISC architecture • 1 KByte, direct mapped instruction cache • Flexible locking mechanism for instruction cache
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MB86933H
40ns/cycle)
MB86933H
MB86933.
instruction set Sun SPARC T3
SPARC v8 architecture BLOCK DIAGRAM
MB86930
MB86931
ADR27
MB86933H-25PF-G-B
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SPARC v9 architecture BLOCK DIAGRAM
Abstract: UltraSPARC ii sparc sparc v7 STP1031LGA Sinak h30
Text: STP1031 July 1997 UltraSPARC -II DATA SHEET Second Generation SPARC v9 64-Bit Microprocessor With VIS DESCRIPTION The STP1031, UltraSPARC–II, is a high-performance, highly-integrated superscalar processor implementing the SPARC-V9 64-bit RISC architecture. The STP1031 is capable of sustaining the execution of up to four
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STP1031
64-Bit
STP1031,
STP1031
STP1031LGA
SPARC v9 architecture BLOCK DIAGRAM
UltraSPARC ii
sparc
sparc v7
STP1031LGA
Sinak h30
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SPARC v9 architecture BLOCK DIAGRAM
Abstract: UltraSPARC ii
Text: STP1031 July 1997 UltraSPARC -II DATA SHEET Second Generation SPARC v9 64-Bit Microprocessor With VIS DESCRIPTION The STP1031, UltraSPARC–II, is a high-performance, highly-integrated superscalar processor implementing the SPARC-V9 64-bit RISC architecture. The STP1031 is capable of sustaining the execution of up to four
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STP1031
STP1031,
64-bit
STP1031
STP1031LGA
SPARC v9 architecture BLOCK DIAGRAM
UltraSPARC ii
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AEG PS 451
Abstract: sun hold RAS 0610 AEG PS 431 relay AEG PS 431 relay manual ras 0610 relay ras 0610 RAS 2415 SUN HOLD TSC701 ras 0610 relay PIN CONFIGURATION relay AEG PS 431
Text: TSC701 Electrical and Mechanical Specifications Preliminary – August 1996 TSC701 This design guide provides no information regarding delivery conditions and availability. Informations contained in specification charts are meant for product description but not as assured characteristics in the legal sense.
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TSC701
17F-1,
AEG PS 451
sun hold RAS 0610
AEG PS 431 relay
AEG PS 431 relay manual
ras 0610 relay
ras 0610
RAS 2415 SUN HOLD
TSC701
ras 0610 relay PIN CONFIGURATION
relay AEG PS 431
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MB86930
Abstract: QFP-208 fujitsu MB86932-20ZF-G MB86932-40ZF-G MB86932
Text: MB86932 930 Series 32–BIT RISC EMBEDDED PROCESSOR MAY 25, 1994 FEATURES • • • • • • • • • • • • • • • • • • • • • • • 40 MHz 25ns/cycle operating frequency SPARCR high performance RISC architecture 8 Kbytes 2-way set associative instruction cache
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MB86932
25ns/cycle)
MB86930
QFP-208 fujitsu
MB86932-20ZF-G
MB86932-40ZF-G
MB86932
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MB86901
Abstract: MB89251 Fujitsu MB86900 mb86900 MB86902 instruction set Sun SPARC T8 MB86931-20ZF-G
Text: MB86931 930 Series 32–BIT RISC EMBEDDED PROCESSOR/ INTERRUPT CONTROLLER/TIMER/USART MAY 24, 1994 FEATURES • 40 MHz 25ns/cycle operating frequency • SPARC high performance RISC processor – 2 Kbytes 2–way set associative instruction and data caches.
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MB86931
25ns/cycle)
MB86901
MB89251
Fujitsu MB86900
mb86900
MB86902
instruction set Sun SPARC T8
MB86931-20ZF-G
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t20s
Abstract: SQFP208 MB86930 MB86936A
Text: MB86936 930 SERIES 32–BIT RISC EMBEDDED PROCESSOR AUGUST, 1996 • JTAG test interface FEATURES • Emulator support hardware • 50 MHz version with clock doubling • SPARC high performance RISC architecture • High Performance SPARC FPU, ANSI/IEEE 754
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MB86936
256Mbyte
t20s
SQFP208
MB86930
MB86936A
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MB86930
Abstract: ADR27
Text: MB86935 930 SERIES 32–BIT RISC EMBEDDED PROCESSOR November 1996 ADVANCE INFORMATION • Parity generation and checking FEATURES • Programmable address decoder and wait-state generator • 66MHz, 80MHz and 100 MHz versions each with clock doubling capability
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MB86935
66MHz,
80MHz
256Mbyte
data15
MB86930
ADR27
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instruction set Sun SPARC T3
Abstract: Sun UltraSparc T2 instruction set Sun SPARC T5 "64-Bit Microprocessor" Sun UltraSparc Sun UltraSparc T1 UltraSPARC ii SUN MICROELECTRONICS SPARC v9 architecture BLOCK DIAGRAM 38b17
Text: STP1031 S un M icro electro nics J u ly 1997 U ltr a S P A R C -!! DATA SHEET Second Generation SPARC v9 64-Bit Microprocessor With VIS D e s c r ip t io n The STP1031, UltraSPARC-II, is a high-perform ance, highly-integrated superscalar processor implementing
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STP1031
64-Bit
STP1031,
STP1031
787-Pin
instruction set Sun SPARC T3
Sun UltraSparc T2
instruction set Sun SPARC T5
"64-Bit Microprocessor"
Sun UltraSparc
Sun UltraSparc T1
UltraSPARC ii
SUN MICROELECTRONICS
SPARC v9 architecture BLOCK DIAGRAM
38b17
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B5110
Abstract: "Bipolar Integrated Technology" B5100 B5210 CA10 instruction set Sun SPARC T6
Text: rff ff /1/s . integrated Blpolar ill II rtm B5100 ËË I T*. Technology, Inc. Advance Information BIT SPARC Floating Point Controller Description Features Fully compatible with the SPARC coprocessor definition interface Supports high performance floating point calculations using
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B5100
B5110/B5120
64-bit
36-bit
B5210
B5110
B5120
MKTG-D011
014123V_
"Bipolar Integrated Technology"
B5100
CA10
instruction set Sun SPARC T6
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TRANSISTOR R 40 AH-16
Abstract: TEA 1091 TRANSISTOR AH-16 sparc v8 AD04M l xd 402 mf xd 402 mf STP1091-60
Text: Prelim inary SPARC Technology Business DATA SHEET D STP1091 _ February 1995 M u lti- C a c h e C ontroller Integrated Cache Controller for SuperSPARC escription The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021
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STP1091
STP1091
STP1020
STP1021
33x8k
TRANSISTOR R 40 AH-16
TEA 1091
TRANSISTOR AH-16
sparc v8
AD04M
l xd 402 mf
xd 402 mf
STP1091-60
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instruction set Sun SPARC T4
Abstract: instruction set Sun SPARC T5 instruction set Sun SPARC T6 L64801 instruction set Sun SPARC T8 DY24D
Text: ABACUS 3170 FLOATING-POINT COPROCESSOR FOR SPARC PRELIMINARY DATA August 1989 Features DIRECT INTERFACE TO MEMORY 20 AND 25 MHz OPERATION FULL COMPLIANCE WITH ANSI/IEEE-754 STANDARD FOR BINARY FLOATING-POINT ARITHMETIC 143-PIN PGA PACKAGE LOW-POWER CMOS SINGLE-CHIP 64-BIT FLOATING-POINT DATA
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64-BIT
S-20/S-25
L64801
ANSI/IEEE-754
143-PIN
instruction set Sun SPARC T4
instruction set Sun SPARC T5
instruction set Sun SPARC T6
instruction set Sun SPARC T8
DY24D
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MB86903
Abstract: instruction set Sun SPARC T3 CY7C601
Text: MB86903 ~ FUJITSU SPARC -BASED IU/FPU AUGUST 1991 DATA SHEET FE A T U R E S _ G E N E R A L D E S C R IP T IO N • Single chip im plementation o f SPARC IU and FPU based upon the SPARC architecture The MB86903 is the first commercially available pro
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MB86903
32-bit
MB86903
instruction set Sun SPARC T3
CY7C601
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Untitled
Abstract: No abstract text available
Text: MB86933 FUJITSU PRELIMINARY SPARClite 32-BIT RISC EMBEDDED PROCESSOR ADVANCE INFORMATION AUGUST 1992 FEATURES G EN ER A L D E S C R IP T IO N • 20 MHz 50ns/cycle operating frequency The MB86933 is the next of the SPARClite series of RISC processors which offers high performance and
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MB86933
32-BIT
50ns/cycle)
MB86933
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MB86933
Abstract: MB86933-20
Text: MB86933 FUJITSU SPARCIite 32-BIT RISC EMBEDDED PROCESSOR MAY 2 5 , 1994 FEATURES_ _ • 20 MHz 50ns/cycle operating frequency • SPARC high performance RISC architecture • 6 window, 104 word register file • Fast interrupt response time
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MB86933
32-BIT
50ns/cycle)
16-bit
MB86933
MB86933-20
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PSA B20 0110
Abstract: Sun UltraSparc T1 UltraSPARC ii ultrasparc
Text: S un M icro electro nics Ju ly 1997 U ltr a S P A R C DATA SHEET -!! Second Generation SPARC v9 64-Bit Microprocessor With VIS D e s c r ip t io n The STP1031, U ltraSPA R C -II, is a high-perform ance, highly-integrated superscalar processor im plem enting
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64-Bit
STP1031,
STP1031
STP1031LGA
PSA B20 0110
Sun UltraSparc T1
UltraSPARC ii
ultrasparc
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Untitled
Abstract: No abstract text available
Text: STP1031 S un M ic r o e l e c t r o n ic s J u ly 1997 UltraSPARC -» DATA SHEET Second Generation SPARC v9 64-Bit Microprocessor With VIS D e s c r ip t io n The STP1031, UltraSPARC-II, is a high-perform ance, highly-integrated superscalar processor implementing
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STP1031
64-Bit
STP1031,
STP1031
787-Pin
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Untitled
Abstract: No abstract text available
Text: M B86936 FUJITSU 930 SERIES 32-BIT RISC EMBEDDED PROCESSOR APRIL, 1996 • On-chip clock generator circuit FEATURES • JTAG test interface • 25 and 50 MHz versions • Emulator support hardware • Clock doubler for 50 MHz version • Single vector trapping
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B86936
32-BIT
256Mbyte
374175b
D01757A
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Untitled
Abstract: No abstract text available
Text: Prelimina: SIARCTechnology STP1090A Business January Multi-Cache Controller ,TM DATA. SE ET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1090A is a high-perform ance external cache controller for the STP1020A SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used w hen a large secondary cache or an interface
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STP1090A
STP1090A
STP1020A
STP1021
33x8k
STP1020H
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MARKING cfk
Abstract: marking code CFK MB86936A
Text: MB86936 FUJITSU 930 SERIES 32-BIT RISC EMBEDDED PROCESSOR AUGUST, 1996 • • • • JTAG test interface Emulator support hardware Single vector trapping Power down modes, with global or selective power down • 0.5 micron gate, 3 level metal CMOS technology,
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MB86936
32-BIT
256Mbyte
MARKING cfk
marking code CFK
MB86936A
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Cy7C601
Abstract: tyn 618 P5H2
Text: PRODUCT DESCRIPTION CYPRESS ~ SEMICONDUCTOR CY7C608 RISC Floating-Point Controller Features • Provides interface between the CY7C601 Integer Unit and CY7C609 Floating-Point Unit • Provides SPARC compatible Floating-Point Arithmetic and registers • Very high performance
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CY7C608
CY7C601
CY7C609
CY7C608-33GC
CY7C608-25GC
tyn 618
P5H2
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64256
Abstract: No abstract text available
Text: DATA SHEET MOS INTEGRATED CIRCUIT ^PD78234 A , 78238(A) 8-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The ¿xPD78234(A)/78238(A) are 78K/II series products. The 78K/II is an 8-bit single-chip microcomputer which can access the memory space of 1M bytes with an external expansion.
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uPD78234
uPD78238
xPD78234
78K/II
juPD78234
IEU-718
IEU-754
PD78234,
64256
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