Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    LP LOG Search Results

    LP LOG Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    X9C303S8IZ-2.7 Renesas Electronics Corporation Logarithmic Digitally Controlled Potentiometer (XDCP™), Terminal Voltage ±5V, 100 Taps, Log Taper, SOICN, /Tube Visit Renesas Electronics Corporation
    X9C303S8IZ Renesas Electronics Corporation Logarithmic Digitally Controlled Potentiometer (XDCP™), Terminal Voltage ±5V, 100 Taps, Log Taper, SOICN, /Tube Visit Renesas Electronics Corporation
    X9C303S8Z Renesas Electronics Corporation Logarithmic Digitally Controlled Potentiometer (XDCP™), Terminal Voltage ±5V, 100 Taps, Log Taper, SOICN, /Tube Visit Renesas Electronics Corporation
    X9C303V8IZ Renesas Electronics Corporation Logarithmic Digitally Controlled Potentiometer (XDCP™), Terminal Voltage ±5V, 100 Taps, Log Taper, TSSOP, /Tube Visit Renesas Electronics Corporation
    X9C303PZ Renesas Electronics Corporation Logarithmic Digitally Controlled Potentiometer (XDCP™), Terminal Voltage ±5V, 100 Taps, Log Taper, PDIP, /Tube Visit Renesas Electronics Corporation

    LP LOG Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: 2 1 THIS COPY IS PROVIDED ON A RESTRICTED BASIS AND IS NOT TO BE USED IN ANY WAY DETRIMENTAL TO THE INTERESTS OF PANDUIT CORP. PANDUIT PART NUMBER MLT2.7WH-LP MLT4WH-LP MLT6WH-LP MLT8WH-LP MLT10WH-LP MLT2.7WH-TL MLT4WH-TL MLT6WH-TL PACKAGE QUANTITY 50 50 50


    Original     		MLT10WH-LP N41122BS/07 N41122BS DC/07A SSECN01037 PDF

    siliconblue

    Abstract: ice40lp 245KB sublvds lvds ICE65 sub-lvds iCE40LP8K-CM225 ICE40LP1K
    Text: iCE40 LP Series Ultra Low-Power mobileFPGA™ Family R SiliconBlue December 15, 2011 1.1 Preliminary Data Sheet Figure 1: iCE40 LP-Series Family Architectural Features  LP-Series - Smartphone targeted series Programmable Logic Block (PLB) optimized for low power


    Original     		iCE40TM iCE65 iCE40 15-DEC-2011) siliconblue ice40lp 245KB sublvds lvds sub-lvds iCE40LP8K-CM225 ICE40LP1K PDF

    ice40lp

    Abstract: ICE40 FPGA sublvds to lvds lp1k BGA 81 ball
    Text: iCE40 LP Series Ultra Low-Power mobileFPGA™ Family March 30, 2012 1.31 Data Sheet Figure 1: iCE40 LP-Series Family Architectural Features  LP-Series - Smartphone targeted series Programmable Logic Block (PLB) optimized for low power 35 µA at f =0 kHz (Typical)


    Original     		iCE40TM iCE65 iCE40 5-MAR-2012 13-FEB-2012 15-DEC-2011 31-OCT-2011 11-JUL-2011 30-MAR-2012) ice40lp ICE40 FPGA sublvds to lvds lp1k BGA 81 ball PDF

    HFBR-0571

    Abstract: 1000BASE-LX 1000BASE-SX AVAGO SFP EVALUATION BOARD
    Text: HFCT-5701L/LP and HFCT-5710L/LP Characterization Report Application Note 5002 Introduction Definition of Terms The HFCT-5701L/LP and HFCT-5710L/LP optical transceivers are fully compliant to the IEEE 802.3 1000BASE-LX and the Fibre Channel specification 100-SM-LC-L respectively.


    Original     		HFCT-5701L/LP HFCT-5710L/LP HFCT-5710L/LP 1000BASE-LX) 100-SM-LC-L 5988-9635EN HFBR-0571 1000BASE-LX 1000BASE-SX AVAGO SFP EVALUATION BOARD PDF

    Untitled

    Abstract: No abstract text available
    Text: iCE40 LP Series Ultra Low-Power mobileFPGA™ Family March 22, 2012 1.3 Data Sheet Figure 1: iCE40 LP-Series Family Architectural Features  LP-Series - Smartphone targeted series Programmable Logic Block (PLB) optimized for low power 35 µA at f =0 kHz (Typical)


    Original     		iCE40â iCE40 iCE65 iCEman40LP 22-MAR-2012) PDF

    Untitled

    Abstract: No abstract text available
    Text: 2 1 THIS COPY IS PROVIDED ON A RESTRICTED BASIS AND IS NOT TO BE USED IN ANY WAY DETRIMENTAL TO THE INTERESTS OF PANDUIT CORP. PANDUIT PART NUMBER MLT2LH-LP MLT4LH-LP MLT6LH-LP MLT8LH-LP .43 [10.9] .335 .020 [8.5] 304 MAXIMUM BUNDLE DIAMETER 2.0" [51] 4.0" [102]


    Original     		N41126BS/04 SSECN01037 N41126BS PDF

    Untitled

    Abstract: No abstract text available
    Text: 2 1 THIS COPY IS PROVIDED ON A RESTRICTED BASIS AND IS NOT TO BE USED IN ANY WAY DETRIMENTAL TO THE INTERESTS OF PANDUIT CORP. PANDUIT PART NUMBER MLT2.7WLH-LP MLT4WLH-LP MLT6WLH-LP MLT8WLH-LP .43 11.0 .335 B 8.5 .020 MAXIMUM BUNDLE DIAMETER 2.7" [69] 4" [102]


    Original     		N41137BS/04 SSECN01042 N41137BS PDF

    IDT VersaClock

    Abstract: No abstract text available
    Text: VERSACLOCK LP USER GUIDE FOR MICROSOFT WINDOWS IDT VERSACLOCK® LP USER GUIDE FOR MICROSOFT WINDOWS© 1 REV C 090310 VERSACLOCK® LP USER GUIDE FOR MICROSOFT WINDOWS© Programmable Clocks - Introduction The VersaClock LP programming software is targeted at enabling novice through experienced PLL designers to easily


    Original     		IDT5V19EExxx IDT5V49EExxx) IDT5P49EExxx) IDT VersaClock PDF

    Untitled

    Abstract: No abstract text available
    Text: 2 1 THIS COPY IS PROVIDED ON A RESTRICTED BASIS AND IS NOT TO BE USED IN ANY WAY DETRIMENTAL TO THE INTERESTS OF PANDUIT CORP. PANDUIT MAX.BUNDLE PACKAGE PART NO. DIA. QTY. MLT2EH-LP 2" [51] 50 MLT4EH-LP 4" [102] 50 MLT6EH-LP 6" [152] 50 MLT8EH-LP 8" [203]


    Original     		MLT10EH-LP MLT12EH-Q N41155BS/04 N41155BS DC/04A SSECN01028 PDF

    Untitled

    Abstract: No abstract text available
    Text: iCE40 LP/HX/LM Family Handbook HB1011 Version 01.2, November 2013 iCE40 LP/HX/LM Family Handbook Table of Contents October 2013 Section I. iCE40 LP/HX Family Data Sheet Introduction Features . 1-1


    Original     		iCE40â HB1011 iCE40 TN1251 PDF

    ICE40 FPGA

    Abstract: ICE40LP1K-CM121 ICE40LP1K ice40lp 225ba ICE40LP1K-CM36 ICE40
    Text: iCE40 LP Series Ultra Low-Power FPGA Family October 03, 2012 1.32 Figure 1: iCE40 LP-Series Family Architectural Features LP-Series - optimized for low power Ultra-small footprints Proven, high-volume 40 nm, low-power CMOS technology I/O Bank 0 I/O Bank 1


    Original     		iCE40TM iCE65 iCE40 5-MAR-2012 13-FEB-2012 15-DEC-2011 31-OCT-2011 11-JUL-2011 03-OCT-2012) ICE40 FPGA ICE40LP1K-CM121 ICE40LP1K ice40lp 225ba ICE40LP1K-CM36 PDF

    Avago qfbr

    Abstract: QFBR Small Form Factor Optical Transceiver for Gigabit Ethernet 1.25 GBd and iSCSI Avago qfbr 57
    Text: HFBR-5701L/LP, HFBR-5710L/LP, HFBR-5730L/LP Small Form Factor Pluggable Optical Transceiver for Gigabit Ethernet 1.25 GBd and Fibre Channel (1.0625 GBd) Data Sheet Description Features The HFBR-5701L optical transceiver is compliant with the specifications set forth in the IEEE802.3 (1000BASE-SX),


    Original     		HFBR-5701L/LP, HFBR-5710L/LP, HFBR-5730L/LP HFBR-5701L IEEE802 1000BASE-SX) 100-M5-SN-I/100-M6-SN-I) HFBR-5710L 1000BASE-SX HFBR-5730L Avago qfbr QFBR Small Form Factor Optical Transceiver for Gigabit Ethernet 1.25 GBd and iSCSI Avago qfbr 57 PDF

    Avago qfbr

    Abstract: No abstract text available
    Text: HFBR-5701L/LP, HFBR-5710L/LP, HFBR-5730L/LP Small Form Factor Pluggable Optical Transceiver for Gigabit Ethernet 1.25 GBd and Fibre Channel (1.0625 GBd) Data Sheet Description Features The HFBR-5701L optical transceiver is compliant with the specifications set forth in the IEEE802.3 (1000BASE-SX),


    Original     		HFBR-5701L/LP, HFBR-5710L/LP, HFBR-5730L/LP HFBR-5701L IEEE802 1000BASE-SX) 100-M5-SN-I/100-M6-SN-I) HFBR-5710L 1000BASE-SX HFBR-5730L Avago qfbr PDF

    AN-39

    Abstract: Power Integrations LNK564 HIGH FREQUENCY Transformer ee19 Transformer ee19 EE16 10 pin bobbin transformers EE19 vertical 6 pin bobbin EE19 bobbin EE10 bobbin EE19 type bobbin
    Text: LinkSwitch-LP Flyback Design Guide Application Note AN-39 thus, dramatically reduces component count and total system cost. Figure 1 shows a LinkSwitch-LP based 2 W power supply without a primary-side clamp. The LinkSwitch-LP family has been optimized to give an approximate CV/CC output


    Original     		AN-39 AN-39 Power Integrations LNK564 HIGH FREQUENCY Transformer ee19 Transformer ee19 EE16 10 pin bobbin transformers EE19 vertical 6 pin bobbin EE19 bobbin EE10 bobbin EE19 type bobbin PDF

    Avago qfbr

    Abstract: QFBR
    Text: HFBR-5701L/LP, HFBR-5710L/LP, HFBR-5730L/LP Small Form Factor Pluggable Optical Transceiver for Gigabit Ethernet 1.25 GBd and Fibre Channel (1.0625 GBd) Data Sheet Description Features The HFBR-5701L optical transceiver is compliant with the specifications set forth in the IEEE802.3 (1000BASE-SX),


    Original     		HFBR-5701L/LP, HFBR-5710L/LP, HFBR-5730L/LP HFBR-5701L IEEE802 1000BASE-SX) 100-M5-SN-I/100-M6-SN-I) HFBR-5710L 1000BASE-SX HFBR-5730L Avago qfbr QFBR PDF

    Untitled

    Abstract: No abstract text available
    Text: 2 1 THIS COPY IS PROVIDED ON A RESTRICTED BASIS AND IS NOT TO BE USED IN ANY WAY DETRIMENTAL TO THE INTERESTS OF PANDUIT CORP. LENGTH MAX BUNDLE PACKAGE "L" .3 [7] QTY DIA. PANDUIT PART NO. MLT2.7WS-LP .43 [10.9] B .24 .01 [6.1] 2.7" [69] 50 MLT4WS-LP MLT6WS-LP


    Original     		N41124BS/10 N41124BS DC/10A SSECN01037 PDF

    JTAG MODULE SPI

    Abstract: spi flash parallel port TSOP 28 SPI memory Package flash 88P8341
    Text: SPI EXCHANGE SPI-3 TO SPI-4 Issue 1.0 FEATURES • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors


    Original     		BH820-1) 88P8341 drw38 JTAG MODULE SPI spi flash parallel port TSOP 28 SPI memory Package flash 88P8341 PDF

    TSOP 48 thermal resistance type1

    Abstract: IDT88P8342 drw22
    Text: SPI EXCHANGE 2 x SPI-3 TO SPI-4 Issue 1.0 FEATURES • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors


    Original     		BH820-1) 88P8342 TSOP 48 thermal resistance type1 IDT88P8342 drw22 PDF

    Untitled

    Abstract: No abstract text available
    Text: iCE40 LP/HX Family Data Sheet DS1040 Version 3.0, July 2014 iCE40 LP/HX Family Data Sheet Introduction February 2014 Data Sheet DS1040 Features  Flexible Logic Architecture – Schmitt trigger inputs, to 200 mV typical hysteresis • Programmable pull-up mode


    Original     		iCE40â DS1040 iCE40 DS1040 iCE40LP1K. PDF

    MT29C1G12

    Abstract: mt29c1g12ma MT29C1G12M MT29C1G smd code AA5 SMD MARKING CODE b21 MT29C2G24MAKLACG-6 smd code U21 marking aa5 mt29c1g1
    Text: Preliminary‡ 152-Ball NAND Flash and LP-DRAM PoP TI OMAP MCP Features NAND Flash and LP-DRAM 152-Ball Package-on-a-Package (PoP) Combination Memory (TI OMAP ) Features • • • • • • Figure 1: Micron NAND Flash and LP-DRAM components RoHS-compliant, “green” package


    Original     		152-Ball 409ng 09005aef8326e5ac 09005aef8326e59a 152ball_ MT29C1G12 mt29c1g12ma MT29C1G12M MT29C1G smd code AA5 SMD MARKING CODE b21 MT29C2G24MAKLACG-6 smd code U21 marking aa5 mt29c1g1 PDF

    TIM-LP-0-000-0

    Abstract: ANTARIS positioning engine IC 7447 16 channel GPS receiver module TIM-LP-0-000 AEK-LS-0-000-0 ASK-LS-0-000-0 ATR0600 DGPS receiver spi tim-lP-9
    Text: TIM-LP GPS Receiver Module ANTARIS Positioning Engine The TIM-LP is an ultra-low power OEM GPS module with built-in low noise amplifier suitable for passive and active antennas. It provides two 3V serial ports, SPI and a set of configurable 3V I/O ports. The TIM-LP provides system resources


    Original     		G3-MS3-02028-G2 TIM-LP-0-000-0 ANTARIS positioning engine IC 7447 16 channel GPS receiver module TIM-LP-0-000 AEK-LS-0-000-0 ASK-LS-0-000-0 ATR0600 DGPS receiver spi tim-lP-9 PDF

    MT29C2G24m

    Abstract: MT29C2G48 MT29C4G48M SMD MARKING CODE h23 MT29F4G16ABC JW256 MT29F4G16AB MT29C2G24MAKLAJG-6 MCP LPDDR 1Gb 512Mb marking k22 SMD
    Text: Preliminary‡ 168-Ball NAND Flash and LP-DRAM PoP TI-OMAP MCP Features NAND Flash and LP-DRAM 168-Ball Package-on-a-Package (PoP) Combination Memory (TI OMAP ) Features • • • • • • Figure 1: Micron NAND Flash and LP-DRAM components RoHS-compliant, “green” package


    Original     		168-Ball 09005aef83071038/PDF: 09005aef83070ff3 168ball MT29C2G24m MT29C2G48 MT29C4G48M SMD MARKING CODE h23 MT29F4G16ABC JW256 MT29F4G16AB MT29C2G24MAKLAJG-6 MCP LPDDR 1Gb 512Mb marking k22 SMD PDF

    IDT88P8344

    Abstract: 88P8344
    Text: SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 FEATURES • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors


    Original     		BH820-1) 88P8344 IDT88P8344 88P8344 PDF

    Untitled

    Abstract: No abstract text available
    Text: iCE40 LP/HX Family Data Sheet DS1040 Version 02.8, February 2014 iCE40 LP/HX Family Data Sheet Introduction February 2014 Data Sheet DS1040 Features – Schmitt trigger inputs, to 200 mV typical hysteresis • Programmable pull-up mode  Flexible Logic Architecture


    Original     		iCE40â DS1040 iCE40 DS1040 iCE40-1K iCE40LP/HX1K iCE40LP640 iCE40LP1K PDF