LSI CELL LIBRARY Search Results

LSI CELL LIBRARY Result Highlights (5)

Part	Manufacturer	Description
DRV2625YFFR	Texas Instruments	Advanced ERM & LRA Haptics Driver with Smart Loop and Embedded Effects Library 9-DSBGA -40 to 85
DRV2625YFFT	Texas Instruments	Advanced ERM & LRA Haptics Driver with Smart Loop and Embedded Effects Library 9-DSBGA -40 to 85
DRV2605YZFT	Texas Instruments	Haptic Driver for ERM/LRA with Built-In Library and Smart Loop Architecture 9-DSBGA -40 to 85
DRV2605YZFR	Texas Instruments	Haptic Driver for ERM/LRA with Built-In Library and Smart Loop Architecture 9-DSBGA -40 to 85
DRV2605LDGSR	Texas Instruments	Haptic Driver for ERM and LRA with Built-In Library and Smart Loop Architecture 10-VSSOP -40 to 85

LSI CELL LIBRARY Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
headland 386 Abstract: transistor zo 607 MA 7S b2211 full subtractor using ic 74138 Text: LOGIC LCB300K Cell-Based 5 Volt ASIC Products Databook October 1994 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.	OCR Scan	LCB300K DB04-000049-00, D-102 I40lg headland 386 transistor zo 607 MA 7S b2211 full subtractor using ic 74138	PDF
G12-l Abstract: LSI Logic ASIC g12 High Voltage G12L g12 transistor G12 000 Text: G12 ASIC Cell-Based Product Features/ Benefits Twelfth Generation ASIC Technology • ASIC technology with 0.18 micron L-drawn Overview LSI Logic’s G12 ASIC Cell-Based product, with its three digital libraries, offers unprecedented options for system ASIC designers to optimize their ASIC or	Original	18-micron 13-micron B20023 G12-l LSI Logic ASIC g12 High Voltage G12L g12 transistor G12 000	PDF
LC97000 Abstract: LC9600 97000Series sanyo lc9600 DIP18 LC90 DIP52 LC92000 Text: SAN YO S E M I C O N D U C T O R CO RP 22E D • 7^707^ QOQbbTñ 1 ■ LC9600Series, 97000Series CM OS LSI Standard Cell 2722A O verview The LC9600, 97000 Series CMOS Standard Cells offer the flexibility and simplicity of semi-custom design using standard cells, together with the convenience of function cell and I/O cell compatibility	OCR Scan	LC9600Series, 97000Series 2722a LC9600, LC9100 LC92000 LC9600 LC97000 DIP64S qip48a sanyo lc9600 DIP18 LC90 DIP52	PDF
ARM1156T2-S Abstract: AMBA AXI to APB BUS Bridge AMBA AXI to APB BUS Bridge architecture PL022 AXI-64 interface ARM processor data flow PL300 AMBA AHB to AXI AMBA AHB bus protocol ARM1156T2S Text: ARM1156T2-S TCM-only Processor with ECC Protection and Reference Design CW001145 FEATURES • 450 MHz timing-closed hardmac OVERVIEW The LSI Logic implementation of the ARM1156T2-S processor for cell-based ASIC provides an integration friendly solution for applications like mass storage	Original	ARM1156T2-S CW001145 ARM966E-S C20069 AMBA AXI to APB BUS Bridge AMBA AXI to APB BUS Bridge architecture PL022 AXI-64 interface ARM processor data flow PL300 AMBA AHB to AXI AMBA AHB bus protocol ARM1156T2S	PDF
ddr phy Abstract: rapidchip LSI coreware library DDR PHY ASIC CW108005 L79301 OC192 LSI Rapidchip Gigablaze serdes CMOS LSI gigablaze serdes Text: RapidChip L79301 StreamSlice™ Configurable 10 Gbit/s Platform Advance Datasheet The StreamSlice L79301 Figure 1 is the first platform of the LSI Logic RapidChip configurable-logic family. It greatly reduces the NRE and development costs usually associated with cell-based logic, while	Original	L79301 80-bit ddr phy rapidchip LSI coreware library DDR PHY ASIC CW108005 L79301 OC192 LSI Rapidchip Gigablaze serdes CMOS LSI gigablaze serdes	PDF
L69301 Abstract: L6930 LSI Rapidchip g12 transistor Text: RapidChip L79301 StreamSlice™ Configurable 10 Gbit/s Platform Advance Datasheet The StreamSlice L79301 Figure 1 is the first platform of the LSI Logic RapidChip configurable-logic family. It greatly reduces the NRE and development costs usually associated with cell-based logic, while	Original	L79301 L79301 80-bit DB08-000215-00 L69301 L6930 LSI Rapidchip g12 transistor	PDF
CMOS Logic Family Specifications Abstract: LSI CMOS GATE ARRAY CB-C9 macro CMOS-N5 Family CMOS8 ic master guide cmos series NEC V30MX CMOS-N5 Gate Array ICs Text: Semi-custom IC , NEC s ASIC Product Line-Up 0.25 m m ASIC What Is ASICs ? Selecting an LSI Gate Array Road Map Criteria for Selection Cell-Based IC Road Map Criteria for Selection Embedded Array Development Period and Relative Performance Development Investment and Element Cost	Original	X13769XJ2V0CD00 EA-C10 CB-C10 CMOS Logic Family Specifications LSI CMOS GATE ARRAY CB-C9 macro CMOS-N5 Family CMOS8 ic master guide cmos series NEC V30MX CMOS-N5 Gate Array ICs	PDF
LSI CMOS GATE ARRAY Abstract: LEA100066 LEA100K LSI LOGIC LEA100K rs flip-flop IC 7400 24008a Text: LSI LOGIC LEA100K Embedded Array Series Description The LEA100K Embedded Array Series is an HCMOS ASIC Application-Specific Integrated Circuit product which combines the integra tion and performance benefits of Cell-Based ASICs with the fast turnaround time of ArrayBased ASICs. The LEA100K series is manufac	OCR Scan	LEA100K LSI CMOS GATE ARRAY LEA100066 LSI LOGIC LEA100K rs flip-flop IC 7400 24008a	PDF
LCA200K Abstract: re 497.1 82385 sim 300 v 703 LCB007 Text: LSI LOGIC NOV 19 1992 LEA200K Embedded Array Series Description The LEA200K Embedded Array Series is a submicron HCMOS ASIC product w hich com bines the integration and performance bene fits of Cell-Based ASICs w ith the fast turnaround time of Array-Based ASICs. The	OCR Scan	LEA200K 55-micron LCA200K re 497.1 82385 sim 300 v 703 LCB007	PDF
lvds to eDP Abstract: qpsk implementation using verilog EDA 2500 manual LSI gigablaze "ASIC Products Databook" vhdl code hamming oak dsp EDP LVDS BZ75 LSI Logic EPBGA Text: G10 -p Deep Submicron ASIC Technology Datasheet The G10-p cell-based CMOS ASIC technology is the highest performance, highest density 3.3 V product in LSI Logic’s portfolio, and supports consumer, computer, and communications applications. The G10-p ASIC product combined with specialized cores enable optimized	Original	G10TM-p G10-p 35-micron lvds to eDP qpsk implementation using verilog EDA 2500 manual LSI gigablaze "ASIC Products Databook" vhdl code hamming oak dsp EDP LVDS BZ75 LSI Logic EPBGA	PDF
LCA200K Abstract: 130 nm CMOS standard cell library 10-JK LEA100K CLDCC LEA200K Text: 5304Û04 ÜD m STl 3bb • LLC LSI LOGIC LEA200K Embedded Array Series Description The LEA200K Embedded Array Series is a submicron HCMOS ASIC product which com bines the integration and performance bene fits of Cell-Based ASICs with the fast turnaround time of Array-Based ASICs. The	OCR Scan	LEA200K 55-micron LCA200K 130 nm CMOS standard cell library 10-JK LEA100K CLDCC	PDF
4x4 barrel shifter with flipflop Abstract: LEA100K LCA100K ta 8259 LEA100006 LEA100008 LSI LOGIC LEA100K 82385 B282 24008A Text: LSI LOGIC LEA100K Embedded Array Series Description The LEA100K Embedded A rray Series is an HCMOS ASIC A pplication-S pecific Integrated Circuit product w hich combines the integra tion and perform ance benefits of Cell-Based ASICs w ith the fa st turnaround tim e of A rrayBased ASICs. The LEA100K series is m anufac	OCR Scan	LEA100K 4x4 barrel shifter with flipflop LCA100K ta 8259 LEA100006 LEA100008 LSI LOGIC LEA100K 82385 B282 24008A	PDF
d217e Abstract: IMX26 7400 signetics input xor IMX86 74LSXX IC ic configuration of xnor gates internal gates of IC 7400 IMX02 7400 signetics 74LS 2 input xnor gate Text: NAPC/ SI G NE TI C S S MC D • bb SBT EH 00 217 20 1 «SIC3 5<+C 217 20 “8 2 5 0 O Ô ' ô ^ S T G ' N j e r r C S ^ ' C Û R P BIPOLAR LSI PR O DU C TS COMPOSITE CELL LOGIC CCL SEMI-CUSTOM FAMILY w ~ T -4 2 -1 1 -0 5 D E S IG N F E A T U R E S The p a ck in g d en sity of an I S L cell (Figure 3) is two to three tim es	OCR Scan	bhS3eI24 QGE172Q T-42-11-05 80-mllliampere -554C d217e IMX26 7400 signetics input xor IMX86 74LSXX IC ic configuration of xnor gates internal gates of IC 7400 IMX02 7400 signetics 74LS 2 input xnor gate	PDF
IC 3-8 decoder 74138 pin diagram Abstract: binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder full adder using Multiplexer IC 74151 ic 74151 ic 74148 block diagram MSI IC 74138 decoder Text: s I SEMICONDUCTOR GROUP 23E D • t?54E40 G00fl535 1 "T-q2-q \ p a rtII CMOS STANDARD CELL LSI MSM91H000 SERIES ¿U S' This M a terial C o p y r i g h t e d B y Its R e s p e c t i v e M a n u f a c t u r e r O K I SEMICONDUCTOR GROUP 23E D ■ b72M240 DGGÔ23b G	OCR Scan	MSM91H000 b72MS40 DQQ023b t-42-41 b724240 IC 3-8 decoder 74138 pin diagram binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder full adder using Multiplexer IC 74151 ic 74151 ic 74148 block diagram MSI IC 74138 decoder	PDF

horizontals output transistor c 6093 Abstract: S1L50552 S1L50000 mod 8 ring counter using JK flip flop i.c t244 working of tsop 1738 application and features of TSOP 1738 level shifter from TTL to CMOS LIN VHDL source code Model 103 Power Supply Text: MF1244-03a GATE ARRAY S1L50000 Series 2.5 Voltage Library DESIGN GUIDE S1L50000 Series 2.5 Voltage Library DESIGN GUIDE First issue April,1998 D Printed June, 2002 in Japan C A NOTICE No part of this material may be reproduced or duplicated in any from or by any means without the	Original	MF1244-03a S1L50000 horizontals output transistor c 6093 S1L50552 mod 8 ring counter using JK flip flop i.c t244 working of tsop 1738 application and features of TSOP 1738 level shifter from TTL to CMOS LIN VHDL source code Model 103 Power Supply	PDF
standard cell library Abstract: jtag samsung Text: STDH90/MDL90 0.35µm 3.3V/5V CMOS Standard Cell Library for Pure Logic/MDL Products STDH90/MDL90 0.35µm 3.3V/5V CMOS Standard Cell Library for Pure Logic/MDL Products Data Book  1998 Samsung Electronics Co., Ltd. All rights reserved. No part of this document may be reproduced, in any form or by any means, without the prior	Original	STDH90/MDL90 STDH90/MDL90 STD90/MDL90) standard cell library jtag samsung	PDF
LSI LOGIC Abstract: 700UM Text: Chip Planning w/ Avant! Planet -PL Workbook G11 Copyright LSI Logic Corporation 1999, 2000 All Rights Reserved. Chip Planning w/ Avant! Planet -PL Software Training Workbook (G11) Produced by the Customer Education Group May 2000 Copyright LSI Logic Corporation 1999, 2000. All rights reserved.	Original		PDF
lsi logic arrays Abstract: No abstract text available Text: L S I L OGI C CORP Û1 dF I 5304Ö0M □ □□□ ÖS 3 7 LSI LSI Logic Corporation 1551 McCarthy Blvd Milpitas, CA 95035 408.433.8000 Telex 172153 The LDS Design System 5304804 General Description ir L S I LOGIC CORP •5T The LDS Design System is a front-end ASIC design	OCR Scan		PDF
1034-01 Abstract: 74 series family LP5080A LP5140A LP7080C LP7080P LP7140P LP7220P Laserpath Corporation lsi logic arrays Text: LSP LASERPATH LP7000P, LP7000C, LP5000A Series Gate Arrays ONE DAY GATE ARRAYS A p ril 1987 Laserpath’s LP7000P, LP7000C, and LP5000A Series are high I/O gate arrays, manufac tured using 2-micron, 2-layer metal HCMOS technology. They have the same electrical	OCR Scan	LP7000P, LP7000C, LP5000A LP7080Pâ LP7080C LP5080A LP5600A 1034-01 74 series family LP5080A LP5140A LP7080C LP7080P LP7140P LP7220P Laserpath Corporation lsi logic arrays	PDF
S3P4 Abstract: LSI Logic Text: L S I LOGIC CORP 54 D e \| S3P4Ô04 OQODOOl □ \| 0 . T_42_05 LSI LOGIC CORPORATION SOFTWARE DATA BOOK LL5000 SERIES Functional Macrocell Library LL5000 Series M acrocell L ib rary fo r M e n to r Graphics ID E A 1000™— Daisy LOGICIAN™ — V a lid Logic SCALDsystem™ E ng ineerin g W orkstations	OCR Scan	LL5000 1000TM-- Tnlm-172 013/384/5K/I/J S3P4 LSI Logic	PDF
KC80 kawasaki Abstract: LSI CMOS Technology z80 vhdl KC80 PGA pin count lsi 176 Text: HIGH-DENSITY KZ300GH KZ300EH CMOS GATE ARRAYS OVERVIEW With the KZ300GH/KZ300EH CMOS Series, Kawasaki LSI offers an advanced, 0.5micron generation of gate arrays and embedded arrays. These leading-edge devices provide optimal solutions to meet your cost and performance needs for low-voltage, high-speed	Original	KZ300GH KZ300EH KZ300GH/KZ300EH 100MHz KC80 kawasaki LSI CMOS Technology z80 vhdl KC80 PGA pin count lsi 176	PDF
LSI CMOS GATE ARRAY Abstract: LSI Logic ASIC Text: CMOS ASIC Translation Of Existing ASIC Designs Introduction It has only been in the last few years that designers and users of application specific integrated circuits ASIC have been able to obtain additional sources for these types of integrated circuits.	Original		PDF
685 35K Abstract: KC80 kawasaki No Turnaround RAM 226 35K zilog z80 z80 vhdl C-111 KC80 "Single-Port RAM" kc80 core Text: HIGH-D ENSITY HIGH-PERFORMANCE KZ4 0 0 G H KZ4 0 0EH CMOS GATE ARRAYS OVERVIEW With the KZ400GH/KZ400EH CMOS Series, Kawasaki LSI offers an advanced generation of 0.35 micron gate arrays and embedded arrays. The Series provides cost-effective solutions for high-speed,	Original	KZ400GH/KZ400EH 685 35K KC80 kawasaki No Turnaround RAM 226 35K zilog z80 z80 vhdl C-111 KC80 "Single-Port RAM" kc80 core	PDF
full subtractor circuit using xor and nand gates Abstract: full subtractor circuit using nor gates 4-bit full adder using nand gates and 3*8 decoder 2 bit magnitude comparator using 2 xor gates 4-bit bcd subtractor 8 bit bcd adder subtractor BCD adder and subtractor half adder using x-OR and NAND gate bcd subtractor full adder circuit using xor and nand gates Text: pASIC Macro Library HIGHLIGHTS More than 350 Architecturally Optimized Macros Includes Simple Gates and Advanced Soft Macros Includes Over 100 7400-Series TTL Building Blocks SpDE Packs as Many as 4 Macros Into a Single Logic Cell SpDE's Logic Optimize maps many simple gates into a single logic cell	Original	7400-Series 10-bit TTL244q TTL259 TTL261 TTL268q full subtractor circuit using xor and nand gates full subtractor circuit using nor gates 4-bit full adder using nand gates and 3*8 decoder 2 bit magnitude comparator using 2 xor gates 4-bit bcd subtractor 8 bit bcd adder subtractor BCD adder and subtractor half adder using x-OR and NAND gate bcd subtractor full adder circuit using xor and nand gates	PDF

LSI CELL LIBRARY Search Results

LSI CELL LIBRARY Result Highlights (5)

LSI CELL LIBRARY Datasheets Context Search

headland 386

G12-l

LC97000

ARM1156T2-S

ddr phy

L69301

CMOS Logic Family Specifications

LSI CMOS GATE ARRAY

LCA200K

lvds to eDP

LCA200K

4x4 barrel shifter with flipflop

d217e

IC 3-8 decoder 74138 pin diagram

horizontals output transistor c 6093

standard cell library

LSI LOGIC

lsi logic arrays

1034-01

S3P4

KC80 kawasaki

LSI CMOS GATE ARRAY

685 35K

full subtractor circuit using xor and nand gates