Untitled
Abstract: No abstract text available
Text: SynTest-Magma Integrated RTL-to-GDSII DFT Flow for ASICs Design-for-Test DFT tools and methodologies enable automation of many aspects of the semiconductor testing process, ensuring that the chip comes through tape-out and manufacturing on time, according to specifications and of good
|
Original
|
|
PDF
|
QFN-88
Abstract: 88 qfn CX6212 CHIPX DDR PHY ASIC 1602 LCD data sheet CX6214 cx6220 pbga 288 0.13um standard cell library
Text: Data Sheet CX6200 Structured ASIC with USB 2.0 HS OTG PHY Product Description The CX6200 product family combines a built-in, silicon-proven, industry standard PHY for USB 2.0 High Speed HS On-the-Go (OTG) with the well-proven X-Cell architecture, to provide industry leading performance using the UMC standard eight-metal 0.13-µm deep
|
Original
|
CX6200
CX6200
CX6000
1-800-95-CHIPX
0210-6K-080-E
QFN-88
88 qfn
CX6212
CHIPX
DDR PHY ASIC
1602 LCD data sheet
CX6214
cx6220
pbga 288
0.13um standard cell library
|
PDF
|
CX50101
Abstract: CX5000 CHIPX CX50211 CX50331 CX50561 CX50841
Text: Product Brief CX5000 0.18 µm Structured ASIC Product Description The CX5000 Structured ASIC family is based on 00.18 µm technology using 3 layers of programmable metal, and supports performance levels up to 200 MHz. The 0.18 µm CX5000 is a Structured ASIC that uses the combination of advanced metal programmable gate array
|
Original
|
CX5000
CX5000
CX50841
1-800-95-CHIPX
0354-5K-070-A
CX50101
CHIPX
CX50211
CX50331
CX50561
CX50841
|
PDF
|
DDR PHY ASIC
Abstract: TCA 290 CX6100 640Mbps CHIPX pbga 288
Text: Product Brief CX6100 Structured ASIC with PCI Express Product Description The CX6100 product family combines a built-in, silicon-proven, industry standard PHY for PCI Express with the well-proven X-Cell architecture, to provide industry leading performance
|
Original
|
CX6100
CX6100
1-800-95-CHIPX
0289-6k-070-C
DDR PHY ASIC
TCA 290
640Mbps
CHIPX
pbga 288
|
PDF
|
QFN-88
Abstract: CX6212 88 qfn DDR PHY ASIC CX6210 1602 KB lcd CHIPX LCD 1602 PLL in RTL Structured
Text: Product Brief CX6200 Structured ASIC with USB 2.0 PHY Product Description The CX6200 product family—a member of the latest generation of Structured ASICs from ChipX—combines built-in, silicon-proven, industry standard PHYs for USB 2.0 High Speed On-the-Go OTG with the well-proven X-Cell Structured ASIC architecture to provide industry
|
Original
|
CX6200
CX6200
Mbps/667
10MHz
0211-6K-070-D
QFN-88
CX6212
88 qfn
DDR PHY ASIC
CX6210
1602 KB lcd
CHIPX
LCD 1602
PLL in RTL
Structured
|
PDF
|
CX3000
Abstract: ASIC CHIPX CX3303
Text: Product Brief CX3000 0.35 µm Structured ASIC Product Description The CX3000 Structured ASIC family is based on 0.35 µm technology using 2 layers of programmable metal, and supports performance levels up to 50 MHz. This family offers cost-effective solutions for designs with legacy requirements, such as 5V tolerance. Using
|
Original
|
CX3000
CX3000
1-800-95-CHIPX
0352-3k-070-A
ASIC
CHIPX
CX3303
|
PDF
|
CX4021
Abstract: ChipX magma asic tool CX4000 CX4101 CX4251
Text: Product Brief CX4000 0.25 µm Structured ASIC Product Description The CX4000 Structured ASIC family is based on 0.25 µm technology using 3 layers of programmable metal, and supports performance levels up to 125 MHz. This family is targeted at a variety of medium performance applications in the consumer, industrial,
|
Original
|
CX4000
CX4000
CX4551
CX4401
1-800-95-CHIPX
0353-4k-070-A
CX4021
ChipX
magma asic tool
CX4101
CX4251
|
PDF
|
CHIPX
Abstract: CX4900 H264
Text: Product Brief CX4900 0.25 µm Standard Cell ASIC/SoC Overview The CX4900 ASIC and System on Chip SoC offering from ChipX combines the well-proven UMC standard six-metal 0.25-µm deep submicron process technology with a rich portfolio of silicon-proven processors, memory structures, analog, I/O and digital IP, and advanced
|
Original
|
CX4900
CX4900
1-800-95-CHIPX
0339-4K-070-A
CHIPX
H264
|
PDF
|
CX6100
Abstract: DDR PHY ASIC CX6104 CX61 CX6113 CHIPX CX6119 cx6112 tca 765
Text: Product Brief CX6100 Structured ASIC with PCI Express Product Description The CX6100 product family combines a built-in, silicon-proven, industry standard PHY for PCI Express with the well-proven X-Cell architecture, to provide industry leading performance
|
Original
|
CX6100
CX6100
Mbps/667
0289-6k-070-D
DDR PHY ASIC
CX6104
CX61
CX6113
CHIPX
CX6119
cx6112
tca 765
|
PDF
|
QFN-88
Abstract: QFN 88 88 qfn CX6212 tfbga CHIPX 658K CX6216 CX620 CX6211
Text: Product Brief CX6200 Structured ASIC with USB 2.0 PHY Product Description The CX6200 product family—a member of the latest generation of Structured ASICs from ChipX—combines built-in, silicon-proven, industry standard PHYs for USB 2.0 High Speed On-the-Go OTG with the well-proven X-Cell Structured ASIC architecture to provide industry
|
Original
|
CX6200
CX6200
CX6000
1-800-95-CHIPX
0211-6K-070-C
QFN-88
QFN 88
88 qfn
CX6212
tfbga
CHIPX
658K
CX6216
CX620
CX6211
|
PDF
|
PCIe PHY
Abstract: CX6800 "PCIe PHY" CHIPX
Text: Product Brief CX6800 Hybrid ASIC Product Description The CX6800 Mixed-signal Hybrid ASIC HA product family combines the benefits of fast turn-around time, low engineering effort and NRE, with the performance and high volume economics of true Standard Cell technology. Within a few weeks, using Hybrid ASIC, companies
|
Original
|
CX6800
1-800-95-CHIPX
0388-6K-070-A
PCIe PHY
"PCIe PHY"
CHIPX
|
PDF
|
ChipX
Abstract: H264 cx-5900
Text: Product Brief CX5900 0.18 µm Standard Cell ASIC/Soc Product Description The CX5900 ASIC and System on Chip SoC offering from ChipX combines the well-proven UMC standard six-metal 0.18-µm deep submicron process technology with a rich portfolio of silicon-proven processors, memory structures, analog, I/O and digital IP, and advanced
|
Original
|
CX5900
CX5900
1-800-95-CHIPX
0340-5K-070-A
ChipX
H264
cx-5900
|
PDF
|
CX6900
Abstract: CHIPX ARM926EJ BA12 0.13um standard cell library CX6000
Text: Product Brief CX6900 0.13 µm Standard Cell ASIC/SoC Overview The CX6900 ASIC and System on Chip SoC offering from ChipX combines the well-proven UMC standard six- or eight-metal 0.13-µm deep submicron process technology with a rich portfolio of silicon-proven processors, memory structures, mixed-signal PHYs, analog, I/O and
|
Original
|
CX6900
CX6900
1-800-95-CHIPX
0341-6k-070-A
CHIPX
ARM926EJ
BA12
0.13um standard cell library
CX6000
|
PDF
|
AC216
Abstract: Core8051 TRISCEND actel core 8051 80C31 ASM51 PQ208 die code actel device intel FPGA Libero
Text: Application Note AC216 Converting Triscend TE5 Designs to Actel Flash-Based FPGAs Introduction: Core8051 and the Actel Flash-Based Family of FPGAs Actel Flash-based FPGA families provide the ultimate way to implement a customizable microcontroller platform. With Core8051 Intellectual Property IP , these versatile and high-performance Flash-based
|
Original
|
AC216
Core8051
8051/52-compatible
programmablee8051
AC216
TRISCEND
actel core 8051
80C31
ASM51
PQ208
die code actel device
intel FPGA
Libero
|
PDF
|
|
EP3SE50
Abstract: Altera source-synchronous wireless encrypt AES DSP
Text: Frequently Asked Questions About Altera Stratix III FPGAs General and What’s New in the Stratix III Family Q1. What is the Stratix III device family? A. Altera® is announcing its new Stratix III device family of lowest-power high-performance FPGAs. Key Features
|
Original
|
65-nm
EP3SE50
Altera source-synchronous
wireless encrypt
AES DSP
|
PDF
|
Untitled
Abstract: No abstract text available
Text: v3.5 ProASICPLUS TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 Million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-Based CMOS Process
|
Original
|
198kbits
|
PDF
|
serial-in serial-out parallel-in
Abstract: schematic diagram online UPS RAM256X9AA ProASICPLUS Flash Family FPGAs v3.5
Text: v3.5 ProASICPLUS TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 Million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-Based CMOS Process
|
Original
|
APA075,
APA150,
APA300
serial-in serial-out parallel-in
schematic diagram online UPS
RAM256X9AA
ProASICPLUS Flash Family FPGAs v3.5
|
PDF
|
RAM256X9SST
Abstract: ProASICPLUS Flash Family FPGAs v5.0
Text: v5.0 ProASICPLUS TM Flash Family FPGAs Features and Benefits • High Capacity High Performance Routing Hierarchy Commercial and Industrial • • • • • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os
|
Original
|
APA075,
APA150,
APA300
RAM256X9SST
ProASICPLUS Flash Family FPGAs v5.0
|
PDF
|
APA075
Abstract: No abstract text available
Text: v4.1 ProASICPLUS TM Flash Family FPGAs Features and Benefits High Capacity Commercial and Industrial • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os Military and Mil-Std 883B • • • 300, 000 to 1 million System Gates
|
Original
|
APA075,
APA150,
APA300
APA075
|
PDF
|
1kx8 static ram
Abstract: No abstract text available
Text: v5.1 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os
|
Original
|
32-Bit
APA075,
APA150,
APA300
1kx8 static ram
|
PDF
|
OB25LPLL
Abstract: diagram LG 21 fs 4 bg model circuits MIL-STD-8831 RAM256X9AA APA075
Text: v5.5 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os
|
Original
|
32-Bit
APA075,
APA150,
APA300
OB25LPLL
diagram LG 21 fs 4 bg model circuits
MIL-STD-8831
RAM256X9AA
APA075
|
PDF
|
Untitled
Abstract: No abstract text available
Text: v5.7 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os
|
Original
|
32-Bit
APA075,
APA150,
APA300
|
PDF
|
schematic diagram UPS 600 Power tree
Abstract: diagram LG 21 fs 4 bg model circuits schematic diagram online UPS
Text: v5.4 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os
|
Original
|
32-Bit
APA075,
APA150,
APA300
schematic diagram UPS 600 Power tree
diagram LG 21 fs 4 bg model circuits
schematic diagram online UPS
|
PDF
|
APA075
Abstract: No abstract text available
Text: v5.2 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os
|
Original
|
32-Bit
APA075,
APA150,
APA300
APA075
|
PDF
|