MARKING TRF Search Results

MARKING TRF Result Highlights (5)

Part	Manufacturer	Description
MG8097/B	Rochester Electronics LLC	8097 - Math Coprocessor - Dual marked (8506301ZA)
5490/BCA	Rochester Electronics LLC	5490 - Decade Counter - Dual marked (M38510/01307BCA)
5405/BCA	Rochester Electronics LLC	5405 - Gate - Dual marked (M38510/00108BCA)
54AC20/SDA-R	Rochester Electronics LLC	54AC20/SDA-R - Dual marked (M38510R75003SDA)
UHD503R/883	Rochester Electronics LLC	UHD503R/883 - Dual marked (5962-8855101CA)

MARKING TRF Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
W55H Abstract: SFSCE10M7WF05 NE604N SMD marking code 55B w55c w55g w55e 3542C W55D R CFXCA450 Text: 通信设备用滤波器 05.01.28 中频用陶瓷滤波器 CERAFILr (kHz, MHz) o kHz SMD型 CFXC_系列 6.5±0.3 (6) (5) (4) 5.2 3.8 EIAJ CODE * (1) (2) (3) Input terminal marking Input terminal marking (5.5) 0.4 1.4 1.9 (3.5) (4.925) 0.5 (5.8) (6) (5) (4)	Original	LFB32130MSQ1A552 LFB32130MSQ1A552 LFB32166MSQ1A527 W55H SFSCE10M7WF05 NE604N SMD marking code 55B w55c w55g w55e 3542C W55D R CFXCA450	PDF
NT6SM32M16AG-S1 Abstract: NT6SM16M32 128M32 NT6SM16M32AK NT6SM32M16AG Lpddr2 Idd1 8M32R NT6SM16M32AK-S1 lpddr2 layout lpddr2 256mb Text: 512Mb LPSDR SDRAM NT6SM32M16AG / NT6SM16M32AK / NT6SM16M32RAK Feature  Options Fully synchronous; all signals registered on positive edge of  Marking VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed	Original	512Mb NT6SM32M16AG NT6SM16M32AK NT6SM16M32RAK -32Meg -16Meg -54-ball -90-ball x13mm) 32M16 NT6SM32M16AG-S1 NT6SM16M32 128M32 Lpddr2 Idd1 8M32R NT6SM16M32AK-S1 lpddr2 layout lpddr2 256mb	PDF
Lpddr2 Idd7 Abstract: COMMAND42 lpddr2 256mb lpddr2 layout NT6SM32M16AG-S2 LPDDR2 1Gb Memory NT6SM16M32 Text: 512Mb LPSDR SDRAM NT6SM32M16AG / NT6SM16M32AK / NT6SM16M32RAK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed	Original	512Mb NT6SM32M16AG NT6SM16M32AK NT6SM16M32RAK -32Meg -16Meg -54-ball -90-ball x13mm) 32M16 Lpddr2 Idd7 COMMAND42 lpddr2 256mb lpddr2 layout NT6SM32M16AG-S2 LPDDR2 1Gb Memory NT6SM16M32	PDF
Lpddr2 Idd7 Abstract: 216-ball LPDDR2 NT6SM16M32 NT6SM16M32AK-S1 Text: 512Mb LPSDR SDRAM NT6SM16M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle	Original	512Mb NT6SM16M32AK -16Meg -90-ball x13mm) 16M32 Lpddr2 Idd7 216-ball LPDDR2 NT6SM16M32 NT6SM16M32AK-S1	PDF
Lpddr2 Idd7 Abstract: Jedec lpddr2 216-ball LPDDR 8Gb lpddr2-s2 Text: 256Mb LPSDR SDRAM NT6SM8M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle	Original	256Mb NT6SM8M32AK -16Meg -54-ball -90-ball x13mm) 16M16 Lpddr2 Idd7 Jedec lpddr2 216-ball LPDDR 8Gb lpddr2-s2	PDF
NTC 200-9 Abstract: a2240 128M16 A1930 NT6SM16M32 Text: 512Mb LPSDR SDRAM NT6SM16M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle	Original	512Mb NT6SM16M32AK -16Meg 16M32 NTC 200-9 a2240 128M16 A1930 NT6SM16M32	PDF
lpddr2 256mb Abstract: NT6DM8M32AC-T1 NT6DM16M16AD NT6DM8M32AC lpddr2 layout NT6DM8M32 Dual LPDDR2 lpddr2 256mb kgd lpddr2-s2 Text: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver Marking  VDD /VDDQ	Original	256Mb NT6DM16M16AD NT6DM8M32AC -16Meg 16M16 lpddr2 256mb NT6DM8M32AC-T1 NT6DM8M32AC lpddr2 layout NT6DM8M32 Dual LPDDR2 lpddr2 256mb kgd lpddr2-s2	PDF
A1930 Abstract: No abstract text available Text: 256Mb LPSDR SDRAM NT6SM8M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle	Original	256Mb NT6SM8M32AK -16Meg 16M16 A1930	PDF
NT6SM16M16AG-S1 Abstract: lpddr2-s2 NT6SM16M16AG NT6SM16M16AG-S1I 128T64 Text: 256Mb LPSDR SDRAM NT6SM16M16AG NT6SM8M32AK Feature Options Fully synchronous; all signals registered on positive edge of z z Marking VDD /VDDQ system clock -1.8V/1.8V M Internal, pipelined operation; column address can be changed z z every clock cycle	Original	256Mb NT6SM16M16AG NT6SM8M32AK -16Meg -54-ball -90-ball x13mm) 16M16 NT6SM16M16AG-S1 lpddr2-s2 NT6SM16M16AG-S1I 128T64	PDF
Untitled Abstract: No abstract text available Text: Data Sheet Rev.1.1 17.11.2010 4096MB DDR3 – SDRAM RDIMM 240 Pin registered DIMM Features: • SGP04G72D1BD2MT-CCRT 4096MB PC3-10600 in FBGA Technology RoHS compliant Options: • Data Rate / Latency DDR3 1333 MT/s CL9 DDR3 1066 MT/s CL7 Marking -CC -BB 	Original	4096MB SGP04G72D1BD2MT-CCRT PC3-10600 240-pin 72-bit	PDF
Untitled Abstract: No abstract text available Text: Data Sheet Rev.1.1 17.11.2010 4096MB DDR3 – SDRAM RDIMM 240 Pin registered DIMM Features: • SGP04G72D1BD2MT-CCRT 4096MB PC3-10600 in FBGA Technology RoHS compliant Options: • Data Rate / Latency DDR3 1333 MT/s CL9 DDR3 1066 MT/s CL7 Marking -CC -BB 	Original	4096MB SGP04G72D1BD2MT-CCRT PC3-10600 240-pin 72-bit	PDF
NT6DM16M Abstract: No abstract text available Text: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver	Original	512Mb NT6DM32M16AD NT6DM16M32AC -32Meg 32M16 -16Meg 16M32 NT6DM16M	PDF
NT6DM32M16AD-T1 Abstract: NT6DM32M16AD NT6DM16M32AC-T1 NT6DM16M32AC NT6DM16M32AC-T3 216-ball NT6DM32M16AD-T3 256M16 lpddr2 256mb lpddr2 layout Text: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver	Original	512Mb NT6DM32M16AD NT6DM16M32AC -32Meg -16Meg -60-ball -90-ball NT6DM32M16AD-T1 NT6DM16M32AC-T1 NT6DM16M32AC NT6DM16M32AC-T3 216-ball NT6DM32M16AD-T3 256M16 lpddr2 256mb lpddr2 layout	PDF
LPDDR 8Gb Abstract: lpddr2 256mb NT6DM32M16AD-T1 NT6DM32M16AD nanya lpddr2 spec Text: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver	Original	512Mb NT6DM32M16AD NT6DM16M32AC -32Meg -16Meg -60-ball -90-ball LPDDR 8Gb lpddr2 256mb NT6DM32M16AD-T1 nanya lpddr2 spec	PDF

Untitled Abstract: No abstract text available Text: Data Sheet Rev.1.0 14.01.2011 1024MB DDR3 – SDRAM UDIMM 240 Pin UDIMM Features: SGU01G64A1BG1SA-xxR • 1GByte in FBGA Technology •      RoHS compliant Options:   Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking -BB	Original	1024MB SGU01G64A1BG1SA-xxR CH-9552	PDF
Untitled Abstract: No abstract text available Text: Data Sheet Rev.1.0 25.02.2011 4096MB DDR3 – SDRAM DIMM 240 Pin UDIMM Features: SGU04G64B1BD2MT-xxR • 4GByte in FBGA Technology •      RoHS compliant Options:    Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking	Original	4096MB SGU04G64B1BD2MT-xxR CH-9552	PDF
Untitled Abstract: No abstract text available Text: Data Sheet Rev.1.1 24.05.2011 2048MB DDR3 – SDRAM UDIMM 240 Pin UDIMM Features: SGU02G64A1BD1MT-xxR • 2GByte in FBGA Technology RoHS compliant Options: • Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking -BB -CC      	Original	2048MB SGU02G64A1BD1MT-xxR CH-9552	PDF
Untitled Abstract: No abstract text available Text: Preliminary‡ 512Mb: x16, x32 Automotive Mobile LPSDR SDRAM Features Automotive Mobile LPSDR SDRAM MT48H32M16LF – 8 Meg x 16 x 4 Banks MT48H16M32LF/LG – 4 Meg x 32 x 4 Banks Features Options Marking • VDD/VDDQ: 1.8V/1.8V • Addressing – Standard addressing option	Original	512Mb: MT48H32M16LF MT48H16M32LF/LG 09005aef8459c827) 09005aef8511d87c	PDF
Untitled Abstract: No abstract text available Text: Data Sheet Rev.1.0 25.02.2011 4096MB DDR3 – SDRAM DIMM 240 Pin UDIMM Features: SGU04G64B1BD2MT-xxR • 4GByte in FBGA Technology •      RoHS compliant Options:    Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking	Original	4096MB SGU04G64B1BD2MT-xxR CH-9552	PDF
Untitled Abstract: No abstract text available Text: Data Sheet Rev.1.1 24.05.2011 2048MB DDR3 – SDRAM UDIMM 240 Pin UDIMM Features: SGU02G64A1BD1MT-xxR • 2GByte in FBGA Technology RoHS compliant Options: • Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking -BB -CC      	Original	2048MB SGU02G64A1BD1MT-xxR CH-9552	PDF
B63URCB Abstract: No abstract text available Text: Data Sheet Rev.1.0 04.02.2011 2048MB DDR3 – SDRAM DIMM 240 Pin UDIMM Features: SGU02G64B1BG2SA-xxR • 2GByte in FBGA Technology •      RoHS compliant Options:  Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking -BB -CC	Original	2048MB SGU02G64B1BG2SA-xxR 240-pin 64-bit PC3-10600 CH-9552 B63URCB	PDF
Untitled Abstract: No abstract text available Text: Data Sheet Rev.1.0 20.11.2010 1GB DDR2 – SDRAM registered DIMM Features: • 240 Pin RDIMM SEP01G72J2BF1SA-30R 1GB PC2-5300 in FBGA Technology RoHS compliant •      Options:  Data Rate / Latency DDR2 533MT/s CL4 DDR2 667MT/s CL5  Marking	Original	SEP01G72J2BF1SA-30R PC2-5300 533MT/s 667MT/s 1024MB 10rlin	PDF
MT48LCM32B2 Abstract: MT48LC2M3B2b5 MT48LCM32B2P MT48LCM32 Micron Technology automotive Text: Preliminary‡ 64Mb: x32 Automotive SDRAM Features Automotive SDR SDRAM MT48LC2M32B2 – 512K x 32 x 4 Banks Features Options Marking • Configuration – 2 Meg x 32 512K x 32 x 4 banks • Plastic package – OCPL on page – 86-pin TSOP II (400 mil) standard	Original	MT48LC2M32B2 PC100-compliant 4096-cycle, 09005aef811ce1fe) 09005aef84d5580d MT48LCM32B2 MT48LC2M3B2b5 MT48LCM32B2P MT48LCM32 Micron Technology automotive	PDF
Untitled Abstract: No abstract text available Text: Data Sheet Rev.1.0 12.12.2012 2048MB DDR3 – SDRAM registered ECC VLP Mini-RDIMM 244 Pin ECC Mini-RDIMM Features: SGH02G72C1BD1MT-XX W RT • •     RoHS compliant Options:  Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking	Original	2048MB SGH02G72C1BD1MT-XX CH-9552 SGH02G72C1BD1MT-xxxRT 2002/96/EC 2011/65/EU	PDF

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MARKING TRF Search Results

MARKING TRF Result Highlights (5)

MARKING TRF Datasheets Context Search

W55H

NT6SM32M16AG-S1

Lpddr2 Idd7

Lpddr2 Idd7

Lpddr2 Idd7

NTC 200-9

lpddr2 256mb

A1930

NT6SM16M16AG-S1

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NT6DM16M

NT6DM32M16AD-T1

LPDDR 8Gb

Untitled

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B63URCB

Untitled

MT48LCM32B2

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