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    onsemi MC10EP51DTG

    IC FF D-TYPE SNGL 1BIT 8TSSOP
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    onsemi MC10E016FNR2G

    IC BINARY COUNTER 8-BIT 28PLCC
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    DigiKey MC10E016FNR2G Cut Tape 385 1
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    onsemi MC10EP105FAG

    IC AND/NAND QUAD 2INP ECL 32LQFP
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    onsemi MC10EL32DG

    IC DIVIDER BY 2 1-BIT 8SOIC
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    onsemi MC10EP52DTG

    IC FF D-TYPE SNGL 1BIT 8TSSOP
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    MC10E Datasheets (500)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    MC10E016 Motorola 8-BIT SYNCHRONOUS BINARY UP COUNTER Original PDF
    MC10E016 On Semiconductor 5.0 V ECL 8-Bit Synchronous Binary Up Counter Original PDF
    MC10E016 On Semiconductor 5V ECL 8-Bit Synchronous Binary Up Counter Original PDF
    MC10E016-D On Semiconductor 5V ECL 8 Bit Synchronous Binary Up Counter Original PDF
    MC10E016FN Motorola 8-Bit Synchronous Binary Up Counter Original PDF
    MC10E016FN On Semiconductor IC COUNTER SINGLE 8-Bit SYNC BIN UP 28PLCC RAIL Original PDF
    MC10E016FNG On Semiconductor IC COUNTER SINGLE 8-Bit SYNC BIN UP 28PLCC RAIL Original PDF
    MC10E016FNR2 On Semiconductor 8-Bit Synch Binary Counter Original PDF
    MC10E016FNR2 On Semiconductor 5 V ECL 8 Bit Synchronous Binary Up Counter Original PDF
    MC10E016FNR2G On Semiconductor IC COUNTER SINGLE 8-Bit SYNC BIN UP 28PLCC T/R Original PDF
    MC10E101 Motorola Quad 4-Input OR/NOR Gate Original PDF
    MC10E101 On Semiconductor 5V ECL Quad 4-Input OR/NOR Gate Original PDF
    MC10E101 On Semiconductor 5V ECL Quad 4-Input OR-NOR Gate Original PDF
    MC10E101-D On Semiconductor 5V ECL Quad 4 Input OR-NOR Gate Original PDF
    MC10E101FN Motorola Quad 4-Input OR/NOR Gate Original PDF
    MC10E101FN On Semiconductor Quad 4-Input OR/NOR Gate Original PDF
    MC10E101FN On Semiconductor Quad 4-Input OR/NOR Gate Original PDF
    MC10E101FN On Semiconductor Quad 4-Input OR/NOR Gate; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37 Original PDF
    MC10E101FN On Semiconductor 5 V ECL Quad 4 Input OR/NOR Gate Original PDF
    MC10E101FN On Semiconductor Quad 4-Input OR/NOR Gate Original PDF
    ...

    MC10E Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    E212 transistor

    Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
    Text: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock


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    PDF MC10E112, MC100E112 MC10E/100E112 MC10E/100E111 r14525 MC10E112/D E212 transistor E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400

    nippon capacitors

    Abstract: DL140 MC100E336 MC10E336
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3ĆBit Registered Bus Transceiver MC10E336 MC100E336 The MC10E/MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs BUS0–BUS2 are specified for driving a 25Ω bus; the receive outputs (Q0 – Q2) are


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    PDF MC10E336 MC100E336 MC10E/MC100E336 1500ps 1000ps MC10E336/D* MC10E336/D DL140 nippon capacitors MC100E336 MC10E336

    marking CODE D2B

    Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
    Text: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be


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    PDF MC10E104, MC100E104 MC10E/100E104 MC10E104FN EIA/JESD78 r14525 MC10E104/D marking CODE D2B MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND

    MC100EP90

    Abstract: MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2
    Text: MC10EP90, MC100EP90 -3.3V / -5VĄTriple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.


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    PDF MC10EP90, MC100EP90 MC10/100EP90 r14525 MC10EP90/D MC100EP90 MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2

    MC100E116

    Abstract: MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116
    Text: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.


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    PDF MC10E116, MC100E116 MC10E/100E116 r14525 MC10E116/D MC100E116 MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116

    KEL04

    Abstract: HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04
    Text: MC10EL04, MC100EL04 5VĄECL 2ĆInput AND/NAND The MC10EL/100EL04 is a 2-input AND/NAND gate. The device is functionally equivalent to the E104 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E104, the EL04 is ideally suited for those


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    PDF MC10EL04, MC100EL04 MC10EL/100EL04 AND8003/D r14525 MC10EL04/D KEL04 HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04

    KEP05

    Abstract: HEP05 MC100EP05 MC10EP05
    Text: MC10EP05, MC100EP05 3.3V / 5VĄECL 2-Input Differential AND/NAND The MC10/100EP05 is a 2–input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance


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    PDF MC10EP05, MC100EP05 MC10/100EP05 LVEL05 LVEL05 r14525 MC10EP05/D KEP05 HEP05 MC100EP05 MC10EP05

    nippon capacitors

    Abstract: DL140 E336 MC100E337 MC10E337
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3ĆBit Scannable Registered Bus Transceiver The MC10E/100E337 is a 3-bit registered bus transceiver with scan. The bus outputs BUS0–BUS2 are specified for driving a 25Ω bus; the receive outputs (Q0 – Q2) are specified for 50Ω. The bus outputs feature


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    PDF MC10E/100E337 MC10E337 MC100E337 DL140 MC10E337/D* MC10E337/D nippon capacitors E336 MC100E337 MC10E337

    MC10EP016

    Abstract: MC100EP016 MC10E016
    Text: MC10EP016, MC100EP016 3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter The MC10/100EP016 is a high−speed synchronous, presettable, cascadeable 8−bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD


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    PDF MC10EP016, MC100EP016 MC10/100EP016 MC10E016 MC10EP016/D MC10EP016 MC100EP016

    EP29

    Abstract: MC100EP29 MC10EP29
    Text: MC10EP29, MC100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset http://onsemi.com Description The MC10/100EP29 is a dual master−slave flip−flop. The device features fully differential Data and Clock inputs as well as outputs.


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    PDF MC10EP29, MC100EP29 MC10/100EP29 MC10/100EL29. MC10EP29/D EP29 MC100EP29 MC10EP29

    MC100E416

    Abstract: MC10E416 MC10E416FN
    Text: MC10E416, MC100E416 5V ECL Quint Differential Line Receiver Description The MC10E416/100E416 is a 5-bit differential line receiving device. The 2.0 GHz of bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators.


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    PDF MC10E416, MC100E416 MC10E416/100E416 MC10E416/D MC100E416 MC10E416 MC10E416FN

    MC100E171

    Abstract: MC10E171 MC10E171FN
    Text: MC10E171, MC100E171 5V ECL 3-Bit 4:1 Multiplexer Description The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to


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    PDF MC10E171, MC100E171 MC10E/100E171 MC10E171/D MC100E171 MC10E171 MC10E171FN

    MC100E151

    Abstract: MC10E151 MC10E151FN
    Text: MC10E151, MC100E151 5V ECL 6-Bit D Register Description The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 or both go HIGH. The asynchronous


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    PDF MC10E151, MC100E151 MC10E/100E151 MC10E151/D MC100E151 MC10E151 MC10E151FN

    MC100E150

    Abstract: MC10E150 MC10E150FN
    Text: MC10E150, MC100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the


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    PDF MC10E150, MC100E150 MC10E/100E150 MC10E150/D MC100E150 MC10E150 MC10E150FN

    KEP16

    Abstract: LVEL16 MC100EP16 MC10EP16
    Text: MC10EP16, MC100EP16 3.3V / 5V ECL Differential Receiver/Driver Description http://onsemi.com MARKING DIAGRAMS* 8 8 1 SOIC−8 D SUFFIX CASE 751 1 8 8 1 Features TSSOP−8 DT SUFFIX CASE 948R • 220 ps Typical Propagation Delay • Maximum Frequency > 4 GHz Typical


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    PDF MC10EP16, MC100EP16 KEP16 HEP16 506AA MC10EP16/D KEP16 LVEL16 MC100EP16 MC10EP16

    IC CD 4030 pin configuration

    Abstract: MC34182D E197 MC10E197 MC10E197FN MC10E197FNR2 root locus applications
    Text: MC10E197 5V ECL Data Separator The MC10E197 is an integrated data separator designed for use in high speed hard disk drive applications. With data rate capabilities of up to 50 Mb/s the device is ideally suited for today’s and future state-of-the-art hard disk designs.


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    PDF MC10E197 MC10E197 MC10E197/D IC CD 4030 pin configuration MC34182D E197 MC10E197FN MC10E197FNR2 root locus applications

    MC100EP35

    Abstract: EL35 HP35 KP35 MC10EP35 code KP35
    Text: MC10EP35, MC100EP35 3.3V / 5V ECL JK Flip−Flop Description The MC10/100EP35 is a higher speed/low voltage version of the EL35 JK flip−flop. The J/K data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and


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    PDF MC10EP35, MC100EP35 MC10/100EP35 HEP35 MC10EP35/D MC100EP35 EL35 HP35 KP35 MC10EP35 code KP35

    E112

    Abstract: E212 MC100E112 MC10E112 E212 transistor
    Text: MC10E112, MC100E112 5V ECL Quad Driver Description The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock


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    PDF MC10E112, MC100E112 MC10E/100E112 MC10E/100E111 MC10E112/D E112 E212 MC100E112 MC10E112 E212 transistor

    MC100E163

    Abstract: MC100E163FN MC100E163FNR2 MC10E163 MC10E163FN MC10E163FNR2
    Text: MC10E163, MC100E163 5VĄECL 2ĆBit 8:1 Multiplexer The MC10E/100E163 contains two 8:1 multiplexers with differential outputs and common select inputs. The select inputs SEL0, 1, 2 control which one of the eight data inputs (A0 – A7, B0 – B7) is propagated to the output.


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    PDF MC10E163, MC100E163 MC10E/100E163 MC10E163FN EIA/JESD78 r14525 MC10E163/D MC100E163 MC100E163FN MC100E163FNR2 MC10E163 MC10E163FN MC10E163FNR2

    E211

    Abstract: MC100E211 MC100E211FN MC100E211FNR2 MC10E211 MC10E211FN MC10E211FNR2 marking code 2b
    Text: MC10E211, MC100E211 5VĄECL 1:6 Differential Clock Distribution Chip The MC10E/100E211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The E211 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed


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    PDF MC10E211, MC100E211 MC10E/100E211 r14525 MC10E211/D E211 MC100E211 MC100E211FN MC100E211FNR2 MC10E211 MC10E211FN MC10E211FNR2 marking code 2b

    HEP58

    Abstract: MC100EP58 MC10EP58
    Text: MC10EP58, MC100EP58 3.3V / 5VĄECL 2:1 Multiplexer The MC10/100EP58 is a 2:1 multiplexer. The device is pin and functionally equivalent to the EL58 and LVEL58 devices. The 100 Series contains temperature compensation. • 310 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical


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    PDF MC10EP58, MC100EP58 MC10/100EP58 LVEL58 HEP58 KEP58 r14525 MC10EP58/D HEP58 MC100EP58 MC10EP58

    MC100E154

    Abstract: MC100E154FN MC100E154FNR2 MC10E154 MC10E154FN MC10E154FNR2
    Text: MC10E154, MC100E154 5VĄECL 5ĆBit 2:1 MuxĆLatch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on


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    PDF MC10E154, MC100E154 MC10E/100E154 MC10E154FN r14525 MC10E154/D MC100E154 MC100E154FN MC100E154FNR2 MC10E154 MC10E154FN MC10E154FNR2

    KEL07

    Abstract: HL-07 E107 MC100EL07 MC10EL07 hl07 IC HEL07
    Text: MC10EL07, MC100EL07 5VĄECL 2ĆInput XOR/XNOR The MC10EL/100EL07 is a 2-input XOR/XNOR gate. The device is functionally equivalent to the E107 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E107, the EL07 is ideally suited for those


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    PDF MC10EL07, MC100EL07 MC10EL/100EL07 AND8003/D r14525 MC10EL07/D KEL07 HL-07 E107 MC100EL07 MC10EL07 hl07 IC HEL07

    transistor BD 889

    Abstract: MC10E1651 MC10E1651FN MC10E1651FNR2 MC10E1651L
    Text: MC10E1651 5V, -5VĄECL Dual ECL Output Comparator with Latch The MC10E1651 is fabricated using ON Semiconductor’s advanced MOSAIC IIIt process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output compatibility with 10 KH logic


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    PDF MC10E1651 MC10E1651 16-pin 20-pin r14525 MC10E1651/D transistor BD 889 MC10E1651FN MC10E1651FNR2 MC10E1651L