Untitled
Abstract: No abstract text available
Text: 74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger Rev. 06 — 4 May 2009 Product data sheet 1. General description The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard
|
Original
|
74AHC132;
74AHCT132
74AHCT132
AHCT132
|
PDF
|
74HC132
Abstract: 74HCT132 74LV132 74LV132BQ 74LV132D 74LV132DB 74LV132N 74LV132PW JESD22-A114E
Text: 74LV132 Quad 2-input NAND Schmitt trigger Rev. 04 — 12 November 2007 Product data sheet 1. General description The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC132 and 74HCT132. The 74LV132 contains four 2-input NAND gates which accept standard input signals.
|
Original
|
74LV132
74LV132
74HC132
74HCT132.
74HCT132
74LV132BQ
74LV132D
74LV132DB
74LV132N
74LV132PW
JESD22-A114E
|
PDF
|
74HC132D
Abstract: Q-100 74HCT132D 74HC132 74HCT132
Text: 74HC132-Q100; 74HCT132-Q100 Quad 2-input NAND Schmitt trigger Rev. 2 — 13 August 2012 Product data sheet 1. General description The 74HC132-Q100; 74HCT132-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with
|
Original
|
74HC132-Q100;
74HCT132-Q100
74HCT132-Q100
HCT132
74HC132D
Q-100
74HCT132D
74HC132
74HCT132
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74AHC132-Q100; 74AHCT132-Q100 Quad 2-input NAND Schmitt trigger Rev. 1 — 8 November 2013 Product data sheet 1. General description The 74AHC132-Q100; 74AHCT132-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with
|
Original
|
74AHC132-Q100;
74AHCT132-Q100
74AHCT132-Q100
AHCT132
|
PDF
|
ahct132
Abstract: 74AHC132 74AHC132BQ 74AHC132D 74AHC132PW 74AHCT132 TSSOP14
Text: 74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger Rev. 06 — 4 May 2009 Product data sheet 1. General description The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard
|
Original
|
74AHC132;
74AHCT132
74AHCT132
AHCT132
74AHC132
74AHC132BQ
74AHC132D
74AHC132PW
TSSOP14
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74LV132-Q100 Quad 2-input NAND Schmitt trigger Rev. 1 — 11 November 2013 Product data sheet 1. General description The 74LV132-Q100 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC132-Q100 and 74HCT132-Q100. The 74LV132-Q100 contains four 2-input NAND gates which accept standard input
|
Original
|
74LV132-Q100
74LV132-Q100
74HC132-Q100
74HCT132-Q100.
74LV132
|
PDF
|
Untitled
Abstract: No abstract text available
Text: INTEGRATED CIRCUITS DATA SHEET 74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger Product specification File under Integrated Circuits, IC06 1999 May 31 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger FEATURES • ESD protection:
|
Original
|
74AHC132;
74AHCT132
EIA/JESD22-A114-A
EIA/JESD22-A115-A
74AHC/AHCT132
245002/01/pp16
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74HC132-Q100; 74HCT132-Q100 Quad 2-input NAND Schmitt trigger Rev. 2 — 13 August 2012 Product data sheet 1. General description The 74HC132-Q100; 74HCT132-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with
|
Original
|
74HC132-Q100;
74HCT132-Q100
74HCT132-Q100
HCT132
|
PDF
|
BLD Schmitt-trigger
Abstract: 74AHC132 74AHC132D 74AHC132PW 74AHCT132 74AHCT132D 74AHCT132PW
Text: INTEGRATED CIRCUITS DATA SHEET 74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger Product specification Supersedes data of 1999 May 31 File under Integrated Circuits, IC06 1999 Sep 24 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger
|
Original
|
74AHC132;
74AHCT132
EIA/JESD22-A114-A
EIA/JESD22-A115-A
EIA/JESD22-C101
245002/02/pp16
BLD Schmitt-trigger
74AHC132
74AHC132D
74AHC132PW
74AHCT132
74AHCT132D
74AHCT132PW
|
PDF
|
74HC132
Abstract: 74HCT132 74LV132 74LV132D 74LV132DB 74LV132N 74LV132PW
Text: 74LV132 Quad 2-input NAND Schmitt trigger Rev. 03 — 15 April 2004 Product data sheet 1. General description The 74LV132 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC132 and 74HCT132. The 74LV132 contains four 2-input NAND gates which accept standard input signals.
|
Original
|
74LV132
74LV132
74HC132
74HCT132.
74HCT132
74LV132D
74LV132DB
74LV132N
74LV132PW
|
PDF
|
PIN DIAGRAM 74hct132
Abstract: 74HC132 74HCT132 74LV132 74LV132BQ 74LV132D 74LV132DB 74LV132N 74LV132PW JESD22-A114E
Text: 74LV132 Quad 2-input NAND Schmitt trigger Rev. 05 — 2 July 2009 Product data sheet 1. General description The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC132 and 74HCT132. The 74LV132 contains four 2-input NAND gates which accept standard input signals.
|
Original
|
74LV132
74LV132
74HC132
74HCT132.
PIN DIAGRAM 74hct132
74HCT132
74LV132BQ
74LV132D
74LV132DB
74LV132N
74LV132PW
JESD22-A114E
|
PDF
|
74HC132
Abstract: 74HCT132
Text: 74HC132; 74HCT132 Quad 2-input NAND Schmitt trigger Rev. 3 — 30 August 2012 Product data sheet 1. General description The 74HC132; 74HCT132 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard
|
Original
|
74HC132;
74HCT132
74HCT132
HCT132
74HC132
|
PDF
|
74AHC132
Abstract: 74AHC132BQ 74AHC132D 74AHC132PW 74AHCT132 TSSOP14
Text: 74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger Rev. 05 — 9 May 2008 Product data sheet 1. General description The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard
|
Original
|
74AHC132;
74AHCT132
74AHCT132
AHCT132
74AHC132
74AHC132BQ
74AHC132D
74AHC132PW
TSSOP14
|
PDF
|
74AHC132
Abstract: 74AHC132BQ 74AHC132D 74AHC132PW 74AHCT132 TSSOP14
Text: 74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger Rev. 04 — 7 February 2005 Product data sheet 1. General description The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . The device is specified in compliance with JEDEC
|
Original
|
74AHC132;
74AHCT132
74AHCT132
74AHC132
74AHC132BQ
74AHC132D
74AHC132PW
TSSOP14
|
PDF
|
|
|