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    MULTILINK CDR DEMUX Search Results

    MULTILINK CDR DEMUX Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TDS4A212MX Toshiba Electronic Devices & Storage Corporation PCI Express switch, 2 Differential Channel, 2:1 multiplexer/1:2 demultiplexer, SPDT, XQFN16 Visit Toshiba Electronic Devices & Storage Corporation
    TDS4B212MX Toshiba Electronic Devices & Storage Corporation PCI Express switch, 2 Differential Channel, 2:1 multiplexer/1:2 demultiplexer, SPDT, XQFN16 Visit Toshiba Electronic Devices & Storage Corporation
    54ACT139/QFA Rochester Electronics LLC 54ACT139 - Dual 1-of-4 Decoder/Demultiplexer Visit Rochester Electronics LLC Buy
    54HC238FK/B Rochester Electronics LLC 54HC238 - 3-8 Line Decoder/Demultiplexer Visit Rochester Electronics LLC Buy
    93L09DM/B Rochester Electronics LLC 93L09 - Multiplexer 2 CRCT 2 x 4:1 MUX/DEMUX Visit Rochester Electronics LLC Buy

    MULTILINK CDR DEMUX Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    Multilink MTC5515

    Abstract: vfo schematic Multilink Technology MTC5515 modulator driver mtc5515 sucoflex 104 mtc1204 MTC1224S multilink cdr demux mtc1203 MTC1224
    Text: MIXED SIGNAL INTEGRATED CIRCUIT PRODUCTS 10 Gb/s reco The MT m C1 16-Bit CDRDMUX Plea mended 204 is no se re fo fer t r new d t o the M esign Applications s. TC1 224 • Telecom transmission systems MTC1204 Product Data Sheet • SONET OC-192 and SDH STM-64 equipment


    Original     		16-Bit MTC1204 OC-192 STM-64 MTC1204 OC-192, STM-64, 03-23-00L Multilink MTC5515 vfo schematic Multilink Technology MTC5515 modulator driver mtc5515 sucoflex 104 MTC1224S multilink cdr demux mtc1203 MTC1224 PDF

    WB4500

    Abstract: telecom bus WB1500 OC48 ORSO82G5 ORT8850 RD1018 STS-48C 30A06 8850H
    Text: Telecom Bus Bridge for SONET Cross Connect March 2004 Reference Design RD1018 Introduction The Telecom Bus Interface TBI is an accepted industry standard that is commonly found in SONET/SDH systems. It is a parallel interface used for chip-to-chip communication on SONET line cards. A typical example illustrating the usefulness of the TBI is shown in Figure 1.


    Original     		RD1018 OC-12 WB1500 ORSO82G5 ORT8850 622Mbps 2488Mbps WB1501 WB4500 telecom bus WB1500 OC48 ORSO82G5 ORT8850 RD1018 STS-48C 30A06 8850H PDF

    A240d

    Abstract: No abstract text available
    Text: Quad, 16-Bit, 2.4 GSPS, TxDAC+ Digital-to-Analog Converter AD9154 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM QUAD MOD ADRF6720-27 DAC RF OUTPUT 0°/90° PHASE SHIFTER JESD204B LPF SYNCOUTx± DAC LO_IN SYSREF QUAD DAC MOD_SPI QUAD MOD ADRF6720-27 DAC RF


    Original     		16-Bit, AD9154 ADRF6720-27 JESD204B Flexi154 AD9154BCPZ AD9154BCPZRL A240d PDF

    XILINX/HD-SDI over sd

    Abstract: CTXIL103 smpte 424m to itu 656 smpte rp 198 3g hd sdi regenerator reclocker smpte 424m to smpte 274m Block diagram on monochrome tv transmitter 54 mhz crystal oscillator XAPP514 2048x1080
    Text: Audio/Video Connectivity Solutions for Virtex-II Pro and Virtex-4 FPGAs Reference Designs for the Broadcast Industry: Volume 1 XAPP514 v4.0.1 October 15, 2008 R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of


    Original     		XAPP514 AES3-2003, UG073: XILINX/HD-SDI over sd CTXIL103 smpte 424m to itu 656 smpte rp 198 3g hd sdi regenerator reclocker smpte 424m to smpte 274m Block diagram on monochrome tv transmitter 54 mhz crystal oscillator XAPP514 2048x1080 PDF

    Untitled

    Abstract: No abstract text available
    Text: Dual, 16-Bit, 2.25 GSPS, TxDAC+ Digital-to-Analog Converter AD9152 Data Sheet FEATURES GENERAL DESCRIPTION Supports input data rates up to 1.125 GSPS Proprietary low spurious and distortion design Single carrier LTE 20 MHz bandwidth BW , ACLR = 77 dBc at 180 MHz IF


    Original     		16-Bit, AD9152 JESD204B CP-56-9) AD9152BCPZ AD9152BCPZRL AD9152-EBZ AD9152-FMC-EBZ AD9152-M6720-EBZ 56-Lead PDF

    AD9136

    Abstract: ad9135
    Text: FEATURES TYPICAL APPLICATION CIRCUIT Support input data rate >2 GSPS Proprietary low spurious and distortion design SFDR = 82 dBc at dc IF, −9 dBFS Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation


    Original     		JESD204B 88-lead ADRF6720 JESD204B AD9136 ad9135 PDF

    Untitled

    Abstract: No abstract text available
    Text: Quad, 16-Bit, 2.8 GSPS, TxDAC+ Digital-to-Analog Converter AD9144 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM Supports input data rate >1 GSPS Proprietary low spurious and distortion design 6-carrier GSM IMD = 77 dBc at 75 MHz IF SFDR = 82 dBc at dc IF, −9 dBFS


    Original     		16-Bit, AD9144 JESD204B MO-220-VRRD 88-Lead CP-88-6) AD9144BCPZ AD9144BCPZRL AD9144-EBZ AD9144-FMC-EBZ PDF

    3080e equivalent

    Abstract: No abstract text available
    Text: ORCA ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSC April 2003 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO82G5 device. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO82G5 is a high-speed transceiver with an aggregate bandwidth of over 20 Gbits/s that is targeted toward users needing high-speed backplane


    Original     		ORSO82G5 ORSO82G5 ORSO82G5-3BM680C ORSO82G5-2BM680C ORSO82G5-1BM680C ORSO82G5-2BM680I ORSO82G5-1BM680I 3080e equivalent PDF

    Untitled

    Abstract: No abstract text available
    Text: ORCA ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs January 2004 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO82G5 device. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO82G5 is a high-speed transceiver with an aggregate bandwidth of over 20 Gbits/s. This device is targeted toward users needing high-speed


    Original     		ORSO82G5 ORSO82G5 ORSO82G5-3BM680C ORSO82G5-2BM680C ORSO82G5-1BM680C ORSO82G5-2BM680I ORSO82G5-1BM680I PDF

    Untitled

    Abstract: No abstract text available
    Text: ORCA ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSC April 2003 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO82G5 device. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO82G5 is a high-speed transceiver with an aggregate bandwidth of over 20 Gbits/s that is targeted toward users needing high-speed backplane


    Original     		ORSO82G5 ORSO82G5 aORSO82G5 ORSO82G5-3BM680C ORSO82G5-2BM680I ORSO82G5-1BM680I PDF

    XAPP1014

    Abstract: smpte 424m to smpte 274m 3G-SDI serializer XAPP224 DATA RECOVERY 425M SMPTE-305M PCIe BT.656 ML571 vhdl code for multiplexing Tables in dvb-t SONY service manual circuits
    Text: Audio/Video Connectivity Solutions for Virtex-5 FPGAs Reference Designs for the Broadcast Industry: Volume 2 XAPP1014 v1.2 November 9, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


    Original     		XAPP1014 XAPP1014 smpte 424m to smpte 274m 3G-SDI serializer XAPP224 DATA RECOVERY 425M SMPTE-305M PCIe BT.656 ML571 vhdl code for multiplexing Tables in dvb-t SONY service manual circuits PDF

    3013X

    Abstract: EQUIVALENT BC 309 3093b
    Text: ORCA ORSO82G5 1.0 - 2.7 Gbps SONET Backplane Interface FPSC October 2002 Preliminary Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO82G5 device. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO82G5 is a high-speed transceiver with an aggregate bandwidth of over 20 Gbits/s that is targeted towards users needing high-speed backplane interfaces for SONET and other non-SONET applications. The ORSO82G5 has 8 channels of integrated 1.02.7G SERDES channels with built-in Clock and Data Recovery (CDR), along with more than 400K usable FPGA


    Original     		ORSO82G5 ORSO82G5 ORT82G5 M-ORSO82G52BM680-DB M-ORSO82G51BM680-DB 3013X EQUIVALENT BC 309 3093b PDF

    L41C

    Abstract: l31c l44c IC L44C DATASHEET L30C L37C L43C l65c ORSO42G5 ORSO82G5
    Text: ORCA ORSO42G5 and ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs March 2004 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO42G5 and


    Original     		ORSO42G5 ORSO82G5 ORSO82G5 ORSO42G5-2BM484I ORSO42G5-1BM484I L41C l31c l44c IC L44C DATASHEET L30C L37C L43C l65c PDF

    30021

    Abstract: L41C 3080c 3080e IC L44C DATASHEET l31c l39c ORSO42G5 ORSO82G5 ORT42G5
    Text: ORCA ORSO42G5 and ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs August 2004 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO42G5 and


    Original     		ORSO42G5 ORSO82G5 ORSO82G5 ORSO42G5 ORSO42G5-2BMN484I 30021 L41C 3080c 3080e IC L44C DATASHEET l31c l39c ORT42G5 PDF

    30021

    Abstract: L48C L41C IC L44C DATASHEET L30C l31c L43C ORSO42G5 ORSO82G5 ORT42G5
    Text: ORCA ORSO42G5 and ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs August 2005 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO42G5 and


    Original     		ORSO42G5 ORSO82G5 ORSO82G5 ORSO42G5-1BMN484I ORSO82G5-2FN680I 30021 L48C L41C IC L44C DATASHEET L30C l31c L43C ORT42G5 PDF

    484-pin BGA

    Abstract: l37c 8 pin DS1028
    Text: ORCA ORSO42G5 and ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs November 2007 Data Sheet DS1028 Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO42G5 and


    Original     		ORSO42G5 ORSO82G5 DS1028 ORSO82G5 402G5 484-pin BGA l37c 8 pin DS1028 PDF

    raychem catalog termination kit and splicing kit

    Abstract: FLUKE 79 3 series DALLAS 2501 220V AC 12V DC regulated switching raychem JOINT procedure KIT BR 8050 D raychem high voltage cable termination kit FLUKE 79 manual APC back UPS RS 800 oz 8602 gn
    Text: EQUIPMENT RENTALS RENT FROM FIS FIS EQUIPMENT RENTALS Our Rental Program has been expanded to include more products, great pricing, and new ways to save! Rent for as little as one week, from the day of shipment until day of return. Needed accessories are included at NO extra charge:


    Original     		MT9083A 18AWG S-RG59ZIP500B S-RG591KB S-RG595000B S-RG59ZIP1KB RG59/U 75ohm raychem catalog termination kit and splicing kit FLUKE 79 3 series DALLAS 2501 220V AC 12V DC regulated switching raychem JOINT procedure KIT BR 8050 D raychem high voltage cable termination kit FLUKE 79 manual APC back UPS RS 800 oz 8602 gn PDF

    3g call flow

    Abstract: XAPP1014 vhdl code for multiplexing table dvb-t SMPTE 296M timing 720p30 smpte 424m to smpte 274m hd-SDI deserializer LVDS 20k preset variable resistor vhdl code for multiplexing Tables in dvb-t ML571 verilog code for interpolation filter
    Text: Audio/Video Connectivity Solutions for Virtex-5 FPGAs Reference Designs for the the Broadcast Industry: Volume 2 Broadcast Industry: Volume 2 [optional] XAPP1014 v1.0 April 29, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


    Original     		XAPP1014 3g call flow XAPP1014 vhdl code for multiplexing table dvb-t SMPTE 296M timing 720p30 smpte 424m to smpte 274m hd-SDI deserializer LVDS 20k preset variable resistor vhdl code for multiplexing Tables in dvb-t ML571 verilog code for interpolation filter PDF

    L211C

    Abstract: 3100B L17c R68T l71c
    Text: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC July 2004 Preliminary Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two


    Original     		8b/10b OIF-SPI4-02 ORSPI4-2FE1036CES ORSPI4-1FE1036CES ORSPI4-2F1156CES ORSPI4-1F1156CES ORSPI4-1FE1036IES ORSPI4-F1156IES L211C 3100B L17c R68T l71c PDF

    L43C

    Abstract: L130C l44c L239C l220c L235C L97c L62C L81C l31c
    Text: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC October 2007 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two


    Original     		8b/10b OIF-SPI4-02 36-Bit 1156-fpBGA 1036-ball 6A-07 1036fpSBGA 1036-ftSBGA) L43C L130C l44c L239C l220c L235C L97c L62C L81C l31c PDF

    L130C

    Abstract: L74c l31c l97c l65c A311TC l146c l48c L202C L235C
    Text: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC May 2009 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two


    Original     		8b/10b OIF-SPI4-02 1156-fpBGA 1036-ball 6A-07 1036fpSBGA 1036-ftSBGA) 06x-09 1036-pin 1036-pin L130C L74c l31c l97c l65c A311TC l146c l48c L202C L235C PDF

    AL437

    Abstract: L97c L235C L103T L41C L140C L94C l165c L239C L43C
    Text: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC November 2003 Preliminary Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two


    Original     		8b/10b OIF-SPI4-02 ORSPI4-1FE1036IES ORSPI4-F1156IES ORSPI4-2FE1036CES ORSPI4-1FE1036CES ORSPI4-2F1156CES ORSPI4-1F1156CES AL437 L97c L235C L103T L41C L140C L94C l165c L239C L43C PDF

    L47C

    Abstract: L146C L135 l54c L62C L97C verilog code of prbs pattern generator L71C L235C L43C
    Text: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC February 2005 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two


    Original     		8b/10b OIF-SPI4-02 ORSPI4-2FE1036I ORSPI4-1FE1036I ORSPI4-2F1156I ORSPI4-1F1156I L47C L146C L135 l54c L62C L97C verilog code of prbs pattern generator L71C L235C L43C PDF

    PIC16F72 inverter ups

    Abstract: UPS inverter PIC16F72 PIC16F676 inverter hex code 16F877 with sd-card and lcd project circuit diagram wireless spy camera NH82801GB xmega-a4 online ups service manual back-ups ES 500 ARM LPC2148 INTERFACING WITH RFID circuit diagram realtek rtd 1186
    Text: the solutions are out there you just haven’t registered yet. RoadTest the newest products in the market! View the latest news, design support and hot new technologies for a range of applications Join the RoadTest group and be in with a chance to trial exclusive new products for free. Plus, read


    Original     		element-14 element14. element14, PIC16F72 inverter ups UPS inverter PIC16F72 PIC16F676 inverter hex code 16F877 with sd-card and lcd project circuit diagram wireless spy camera NH82801GB xmega-a4 online ups service manual back-ups ES 500 ARM LPC2148 INTERFACING WITH RFID circuit diagram realtek rtd 1186 PDF