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    PIN ASSIGNMENT LVDS Search Results

    PIN ASSIGNMENT LVDS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CS-DSDMDB09MF-010 Amphenol Cables on Demand Amphenol CS-DSDMDB09MF-010 9-Pin (DB9) Deluxe D-Sub Cable - Copper Shielded - Male / Female 10ft Datasheet
    CS-DSDMDB15MF-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB15MF-002.5 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Female 2.5ft Datasheet
    CS-DSDMDB15MM-025 Amphenol Cables on Demand Amphenol CS-DSDMDB15MM-025 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Male 25ft Datasheet
    CS-DSDMDB25MM-010 Amphenol Cables on Demand Amphenol CS-DSDMDB25MM-010 25-Pin (DB25) Deluxe D-Sub Cable - Copper Shielded - Male / Male 10ft Datasheet
    CS-DSDMDB37MM-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB37MM-002.5 37-Pin (DB37) Deluxe D-Sub Cable - Copper Shielded - Male / Male 2.5ft Datasheet

    PIN ASSIGNMENT LVDS Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    LVDS 30 pin hirose LVDS

    Abstract: LVDS 30 pin hirose connector LVDS LVDS 30 pin hirose connector df14 LVDS 26 pin hirose LVDS LVDS connector 30 pin lvds 26 pin OUT03 4164702-10 LVDS connector 26 pin VLCD12
    Text: 4164702-10 LVDS Add On Board The LVDS add-on board of P/N : 4164702-10 designs for single pixel LVDS panel. Mechanical drawing 4164702-10 Connector pin assignment : CN5 – Panel connector: HIROSE DF14-20P-1.25 PIN SYMBOL 1 VLCD 2 VLCD 3 GND 4 GND 5 /OUT00


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    DF14-20P-1 /OUT00 OUT00 /OUT01 OUT01 /OUT02 OUT02 /OUT03 OUT03 DF11-28DS-2DSA LVDS 30 pin hirose LVDS LVDS 30 pin hirose connector LVDS LVDS 30 pin hirose connector df14 LVDS 26 pin hirose LVDS LVDS connector 30 pin lvds 26 pin 4164702-10 LVDS connector 26 pin VLCD12 PDF

    top mark QA1

    Abstract: ICS843S2807 ICS843S2807BY MS-026 Nippon capacitors
    Text: PRELIMINARY ICS843S2807 FEMTOCLOCK CRYSTAL-TOLVPECL/LVDS/LVCMOS CLOCK GENERATOR • Maximum output frequency: 350MHz VCCO_LVCMOS QA0 VEE QB1 • Crystal input frequency: 25MHz QB0 PIN ASSIGNMENT VCCO_LVCMOS • Five banks of outputs: Bank A: one single-ended QA0 LVCMOS output at: 133MHz


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    ICS843S2807 350MHz 25MHz 133MHz 67MHz, 100MHz 125MHz 50MHz top mark QA1 ICS843S2807 ICS843S2807BY MS-026 Nippon capacitors PDF

    Untitled

    Abstract: No abstract text available
    Text: LVDS Driver and Receiver MODULE 4 Lines-SOP Low-voltage differential signaling Driver and Receiver MODULE 3DLV3304VS1374 3V Quad Driver and Receiver, based on Quad Pin Assignment Top View SOP 34 (Pitch : 0.65 mm) Features • • • • • • • •


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    3DLV3304VS1374 ANSI/TIA/EIA-644 3DFP-0374-REV PDF

    3DLV3304VS1374

    Abstract: 23/3D Plus
    Text: LVDS Driver and Receiver MODULE 4 Lines-SOP Low-voltage differential signaling Driver and Receiver MODULE 3DLV3304VS1374 3V Quad Driver and Receiver, based on Quad Pin Assignment Top View SOP 34 (Pitch : 0.65 mm) Features •       


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    3DLV3304VS1374 ANSI/TIA/EIA-644 3DFP-0374-REV 3DLV3304VS1374 23/3D Plus PDF

    Untitled

    Abstract: No abstract text available
    Text: LVDS Receiver MODULE 8 Lines-SOP 3DLV3208VS1373 Low-voltage differential signaling Receiver MODULE 3V Eight Line Receivers, based on Quad Pin Assignment Top View SOP 34 (Pitch : 0.65 mm) Features • • • • • • • • • • >400 Mbps (200 MHz) switching rates


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    3DLV3208VS1373 ANSI/TIA/EIA-644 3DLV3208VS1373 3DFP-0373-REV PDF

    Untitled

    Abstract: No abstract text available
    Text: LVDS Receiver MODULE 8 Lines-SOP 3DLV3208VS1373 Low-voltage differential signaling Receiver MODULE 3V Eight Line Receivers, based on Quad Pin Assignment Top View SOP 34 (Pitch : 0.65 mm) Features •           >400 Mbps (200 MHz) switching rates


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    3DLV3208VS1373 ANSI/TIA/EIA-644 3DLV3208VS1373 3DFP-0373-REV PDF

    Untitled

    Abstract: No abstract text available
    Text: LVDS Driver MODULE 8 Lines-SOP 3DLV3108VS1372 Low-voltage differential signaling Driver MODULE 3V Eight Line Drivers, based on Quad Pin Assignment Top View SOP 34 (Pitch : 0.65 mm) Features • • • • • • • • • • • >400 Mbps (200 MHz) switching rates


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    3DLV3108VS1372 ANSI/TIA/EIA-644 3DLV3108VS1372 3DFP-0372-REV PDF

    Untitled

    Abstract: No abstract text available
    Text: LVDS Receiver MODULE 8 Lines-SOP 3DLV3208VS1373 Low-voltage differential signaling Receiver MODULE 3V Eight Line Receivers, based on Quad Pin Assignment Top View SOP 34 (Pitch : 0.65 mm) Features •            >400 Mbps (200 MHz) switching rates


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    3DLV3208VS1373 ANSI/TIA/EIA-644 3DFP-0373-REV PDF

    3DLV3108VS1372

    Abstract: 20/3DLV3108VS1372
    Text: LVDS Driver MODULE 8 Lines-SOP 3DLV3108VS1372 Low-voltage differential signaling Driver MODULE 3V Eight Line Drivers, based on Quad Pin Assignment Top View SOP 34 (Pitch : 0.65 mm) Features •            >400 Mbps (200 MHz) switching rates


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    3DLV3108VS1372 ANSI/TIA/EIA-644 3DFP-0372-REV 3DLV3108VS1372 20/3DLV3108VS1372 PDF

    M1010-01

    Abstract: M2000 134Hz
    Text: Preliminary Information Integrated Circuit Systems, Inc. M1010-01 VCSO BASED CLOCK JITTER ATTENUATOR GENERAL DESCRIPTION PIN ASSIGNMENT 9 x 9 mm SMT 27 26 25 24 23 22 21 20 19 FIN_SEL1 GND NC DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC The M1010-01 is a VCSO (Voltage Controlled SAW


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    M1010-01 M1010-01 OC-12 OC-48 29Sep2003 M2000 134Hz PDF

    M1021

    Abstract: M1020 315HZ GR-253 M2000 M1021-11-155 M102-01
    Text: Preliminary Information Integrated Circuit Systems, Inc. M1020/21 VCSO BASED CLOCK PLL GENERAL DESCRIPTION PIN ASSIGNMENT 9 x 9 mm SMT 27 26 25 24 23 22 21 20 19 MR_SEL3 GND NC DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC The M1020/21 is a VCSO (Voltage Controlled SAW


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    M1020/21 M1020/21 11Nov2003 M1021 M1020 315HZ GR-253 M2000 M1021-11-155 M102-01 PDF

    Untitled

    Abstract: No abstract text available
    Text: Product Data Sheet Integrated Circuit Systems, Inc. M2020/21 VCSO BASED CLOCK PLL PIN ASSIGNMENT 9 x 9 mm SMT FIN_SEL1 GND P_SEL2 DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC GENERAL DESCRIPTION 27 26 25 24 23 22 21 20 19 The M2020/21 is a VCSO (Voltage Controlled SAW


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    M2020/21 M2020/21 20Jul2009 PDF

    OTU1

    Abstract: No abstract text available
    Text: Product Data Sheet Integrated Circuit Systems, Inc. M2006-02 VCSO BASED FEC CLOCK PLL GENERAL DESCRIPTION PIN ASSIGNMENT 9 x 9 mm SMT 27 26 25 24 23 22 21 20 19 FIN_SEL1 GND NC DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC The M2006-02 is a VCSO (Voltage Controlled SAW


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    M2006-02 M2006-02 13Jul2004 OTU1 PDF

    10Gb CDR

    Abstract: M2050 GR-253 M2051 M2052 TTL LVDS
    Text: M2050/51/52 Preliminary Information Integrated Circuit Systems, Inc. SAW PLL FOR 10GBE 64B/66B FEC GENERAL DESCRIPTION PIN ASSIGNMENT 9 x 9 mm SMT 27 26 25 24 23 22 21 20 19 FIN_SEL1 GND P_SEL2 DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC The M2050/51/52 is a VCSO (Voltage Controlled SAW


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    M2050/51/52 10GBE 64B/66B M2050/51/52 64b/66b. M2050 M2051 M2052 10Gb CDR M2050 GR-253 M2051 M2052 TTL LVDS PDF

    lvds connectors pin assignments

    Abstract: cna 450 spice simulation
    Text: May 2001, ver. 1.0 Introduction LVDS Signaling Using APEX Device I/O Pins Application Note 138 Density increases in programmable logic devices PLDs have led users to integrate more functions into today's PLDs. This increase in functionality has allowed PLDs to play a major role in transmitting data between


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    TIA/EIA-644 lvds connectors pin assignments cna 450 spice simulation PDF

    Untitled

    Abstract: No abstract text available
    Text: AND150X4L06-HB 15.0” XGA Color TFT LCD Module Features • 15.0” XGA color display 1024 x 768 pixels that can displays 16.2M colors • DE (Data Enable) only mode • LVDS Interface with 1 pixel/clock • Optimum viewing angle is at 6 o’clock direction


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    AND150X4L06-HB DF19K-20P-1H DF19-20S-1C BHR-03VS-1 SM02B-BHS-1-TB PDF

    Untitled

    Abstract: No abstract text available
    Text: FIN1027 / FIN1027A — 3.3V LVDS, 2-Bit, High-Speed, Differential Driver Description Features ̇ ̇ ̇ ̇ ̇ ̇ ̇ ̇ This dual driver is designed for high-speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The driver translates LVTTL signal


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    FIN1027 FIN1027A 350mV, 600Mbs FIN1027A FIN1028, PDF

    CH7308

    Abstract: CH7308A AN8326 Chrontel CH7308 AN83 CHRONTEL Si4953 10UF 24C16 2N7002
    Text: AN-83 Chrontel CHRONTEL CHRONTEL CHRONTEL Application Notes PCB Layout and Design Considerations for the CH7308 SDVO LVDS Transmitter 1. Introduction This application note focuses on the basic PCB layout and design guidelines for the CH7308 LVDS Output Device with


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    AN-83 CH7308 CH7308A AN8326 Chrontel CH7308 AN83 CHRONTEL Si4953 10UF 24C16 2N7002 PDF

    Untitled

    Abstract: No abstract text available
    Text: AN 522: Implementing Bus LVDS Interface in Supported Altera Device Families AN-522-2.2 Application Note This application note describes how to implement the Bus LVDS BLVDS interface in the supported Altera device families for high-performance multipoint


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    AN-522-2 PDF

    SDVB

    Abstract: PM5312 PM5355 S3045
    Text: DEVICE SPECIFICATION SONET/SDH OC-12 TO OC-48 MUX/DEMUX SONET/SDH OC-12 TO OC-48 MUX/DEMUX S3045 S3045 APPLICATIONS FEATURES • Complies with Bellcore and ITU-T specifications • Supports STS-12/STM-4 to STS-48/STM-16 Mux/Demux functions • 8-bit LVDS data path for STS-48/STM-16 data


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    OC-12 OC-48 S3045 STS-12/STM-4 STS-48/STM-16 STS-48/STM-16 SDVB PM5312 PM5355 S3045 PDF

    DONG YANG power supply

    Abstract: FCI Electronics laser diode toshiba transistor nc STM-64
    Text: March 2001 Optical Communication Devices 10 Gb/s Optical Transponder TOTR370M Series PRELIMINARY APPLICATION • SONET / SDH (OC-192 / STM-64) applications FEATURES Gb/s optical transceiver with 16:1 MUX/DMUX • 10 LVDS 622 Mb/s data and 622 MHz clock • Differential


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    OTR370M OC-192 STM-64) TxDATA15 DONG YANG power supply FCI Electronics laser diode toshiba transistor nc STM-64 PDF

    Untitled

    Abstract: No abstract text available
    Text: DEVICE SPECIFICATION > 4M C SONET/SDH OC-12 TO OC-48 MUX/DEMUX FEATURES • Complies with ANSI, Bellcore and ITU-T specifications • Supports STS-12/STM-4 to STS-48/STM-16 Mux/Demux functions • 8-bit LVDS data path for STS-48/STM-16 data • 8-bit LVTTL data path with parity for each


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    S3045 OC-12 OC-48 STS-12/STM-4 STS-48/STM-16 S3041/S3042 PM5355 PM5312 PDF

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY SPECIFICATION J FEATURES C C GENERAL DESCRIPTION Micro-power Bipolar technology Complies with ANSI, Bellcore, and ITU-T specifications On-chip high-frequency PLL for clock generation Supports 2.4 GHz OC-48 Reference frequency of 155.52 MHz 8-bit LVDS data path


    OCR Scan
    OC-48) S3041 OC-48 PDF

    S3047

    Abstract: U311D XS-3045
    Text: PRELIMINARY DEVICE SPECIFICATION > 4 M C SO N E T/SD H O C -12 TO OC-48 MUX/DEIWUX FEATURES • Complies with ANSI, Bellcore and ITU-T specifications • Supports STS-12/STM-4 to STS-48/STM-16 Mux/Demux functions • 8-bit LVDS data path for STS-48/STM-16 data


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    OC-48 S3045 STS-12/STM-4 STS-48/STM-16 S3041/S3042 PM5355 PM5312 311CLKINP S3047 U311D XS-3045 PDF