Untitled
Abstract: No abstract text available
Text: SY89297U 2.5/3.3V, 3.2Gbps Precision CML DualChannel Programmable Delay General Description The SY89297U is a DC-3.2Gbps programmable, twochannel delay line. Each channel has a delay range from 2ns to 7ns 5ns delta delay in programmable increments as small as 5ps. The delay step is extremely linear and
|
Original
|
PDF
|
SY89297U
SY89297U
10-bits.
M9999-022509-C
|
Untitled
Abstract: No abstract text available
Text: SY89297U 2.5V, 3.2Gbps Precision CML Dual-Channel Programmable Delay Rev. 04/15/08-A3 General Description The SY89297U is a DC-3.2Gbps programmable, twochannel delay line. Each channel has a delay range from 2ns to 7ns 5ns delta delay in programmable increments
|
Original
|
PDF
|
SY89297U
04/15/08-A3
SY89297U
10-bits.
M9999-041508-A
|
dnr14d
Abstract: circuit diagram of 7.1 surround sound pin diagram 16x16 LED matrix display MR60 A835M 6sr5 MR601
Text: a High Quality 8-bit PAL/NTSC Video Encoder with six DAC outputs ADV7190 Preliminary Technical Data Programmable VBI Vertical Blanking Interval Programmable Sub-Carrier Frequency and Phase. Programmable LUMA Delay Programmable CHROMA Delay Programmable Gamma Correction
|
Original
|
PDF
|
10-Bit
ADV7190
64-LEAD
ST-64)
dnr14d
circuit diagram of 7.1 surround sound
pin diagram 16x16 LED matrix display
MR60
A835M
6sr5
MR601
|
PDU13F
Abstract: PDU13F-1 PDU13F-10 PDU13F-15 PDU13F-2 PDU13F-20 PDU13F-3 PDU13F-5
Text: PDU13F data 3 delay devices, inc. 3-BIT PROGRAMMABLE DELAY LINE SERIES PDU13F FEATURES • • • • • • • • PACKAGES Digitally programmable in 8 delay steps Monotonic delay-versus-address variation Two separate outputs: inverting & non-inverting
|
Original
|
PDF
|
PDU13F
PDU13F)
14-pin
PDU13F
PDU13F-1
PDU13F-10
PDU13F-15
PDU13F-2
PDU13F-20
PDU13F-3
PDU13F-5
|
Untitled
Abstract: No abstract text available
Text: PDU18F FEATURES • • • • • • • • data 3 delay devices, inc. 8-BIT PROGRAMMABLE DELAY LINE SERIES PDU18F PACKAGES Digitally programmable in 256 delay steps Monotonic delay-versus-address variation Two separate outputs: inverting & non-inverting
|
Original
|
PDF
|
PDU18F
|
Untitled
Abstract: No abstract text available
Text: PDU16F data 3 delay devices, inc. 6-BIT PROGRAMMABLE DELAY LINE SERIES PDU16F FEATURES • • • • • • • • PACKAGES Digitally programmable in 64 delay steps Monotonic delay-versus-address variation Two separate outputs: inverting & non-inverting
|
Original
|
PDF
|
PDU16F
PDU16F)
24-pin
PDU16F-xx
|
PDU138
Abstract: PDU138-1 PDU138-10 PDU138-12 PDU138-15 PDU138-2 PDU138-20 PDU138-5
Text: PDU138 data 3 delay devices, inc. 3-BIT PROGRAMMABLE DELAY LINE SERIES PDU138 FEATURES • • • • • • • PACKAGES Digitally programmable in 8 delay steps Monotonic delay-versus-address variation Precise and stable delays Input & outputs fully TTL interfaced & buffered
|
Original
|
PDF
|
PDU138
PDU138)
16-pin
PDU138-xx
PDU138-xxM
PDU138-series
PDU138
PDU138-1
PDU138-10
PDU138-12
PDU138-15
PDU138-2
PDU138-20
PDU138-5
|
PDU53
Abstract: TAIS SMD PDU53-100 PDU53-1000 PDU53-200 PDU53-250 PDU53-400 PDU53-500 PDU53-750
Text: PDU53 data 3 delay devices, inc. 3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE SERIES PDU53 FEATURES • • • • • PACKAGES Digitally programmable in 8 delay steps Monotonic delay-versus-address variation Precise and stable delays Input & outputs fully 100K-ECL interfaced & buffered
|
Original
|
PDF
|
PDU53
PDU53)
100K-ECL
16-pin
PDU53-xx
PDU53-xxM
PDU53-xxC3
100ns
PDU53
TAIS SMD
PDU53-100
PDU53-1000
PDU53-200
PDU53-250
PDU53-400
PDU53-500
PDU53-750
|
Untitled
Abstract: No abstract text available
Text: PDU1064H data 3 delay devices, inc. 6-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE SERIES PDU1064H FEATURES • • • • • PACKAGES Digitally programmable in 64 delay steps Monotonic delay-versus-address variation Precise and stable delays Input & outputs fully 10KH-ECL interfaced & buffered
|
Original
|
PDF
|
PDU1064H
PDU1064H)
10KH-ECL
48-pin
|
9.1 b2
Abstract: 74LS family delay line programmable delay line 74F04 DS1045 DS1045-2 DS1045-3 DS1045-4 DS1045-5
Text: DS1045 DS1045 4-Bit Dual Programmable Delay Line FEATURES PIN ASSIGNMENT • All–silicon time delay • Two programmable outputs from a single input produce output–to–output delays between 9 and 84 ns depending on device type • Programmable via four input pins
|
Original
|
PDF
|
DS1045
9.1 b2
74LS family
delay line
programmable delay line
74F04
DS1045
DS1045-2
DS1045-3
DS1045-4
DS1045-5
|
Untitled
Abstract: No abstract text available
Text: Micrel, Inc. 2.5V/3.3V 1.5GHz PRECISION LVPECL PROGRAMMABLE DELAY WITH FINE TUNE CONTROL Precision Edge ® SY89296U Precision Edge SY89296U FEATURES • Precision LVPECL programmable delay line ■ Guaranteed AC performance over temperature and voltage:
|
Original
|
PDF
|
SY89296U
SY89296U
160ps
10psPP
MC100EP195
40ps/V
M9999-011806
|
Untitled
Abstract: No abstract text available
Text: Micrel 2.5V/3.3V 1.5GHz PRECISION LVPECL PROGRAMMABLE DELAY WITH FINE TUNE CONTROL Precision Edge SY89296U Precision Edge™ SY89296U FEATURES • Precision LVPECL programmable delay line ■ Guaranteed AC performance over temperature and voltage: • > 1.5GHz fMAX
|
Original
|
PDF
|
SY89296U
SY89296U
160ps
10psp-p
MC100EP195
40ps/V
32-pincation
M9999-120703
|
Untitled
Abstract: No abstract text available
Text: Micrel 2.5V/3.3V 1.5GHz PRECISION LVPECL PROGRAMMABLE DELAY WITH FINE TUNE CONTROL Precision Edge SY89296U Precision Edge™ SY89296U FEATURES • Precision LVPECL programmable delay line ■ Guaranteed AC performance over temperature and voltage: • > 1.5GHz fMAX
|
Original
|
PDF
|
SY89296U
160ps
MC100EP195
40ps/V
M9999-103003
|
Untitled
Abstract: No abstract text available
Text: Micrel 2.5V/3.3V 1.5GHz PRECISION LVPECL PROGRAMMABLE DELAY Precision Edge SY89295U Precision Edge™ SY89295U FEATURES • Precision LVPECL programmable delay line ■ Guaranteed AC performance over temperature and voltage: • > 1.5GHz fMAX • < 160ps rise/fall times
|
Original
|
PDF
|
SY89295U
160ps
MIC100EP195
M9999-103003
|
|
EP9450-6
Abstract: EP9450-7 EP9450-8 EP9450-9 EP9450-1 EP9450-10 EP9450-15 EP9450-2 EP9450-3 EP9450-4
Text: 16 Pin DIL 3 Bit Programmable ECL Delay Lines DELAYS AND TOLERANCES in nS PART NUMBER MINIMUM DELAY (Inherent) MAX IMUM DELAY EP9450-1 EP9450-2 EP9450-3 EP9450-4 EP9450-5 EP9450-6 EP9450-7 EP9450-8 EP9450-9 EP9450-10 EP9450-15 EP9450-20 EP9450-25 EP9450-30
|
Original
|
PDF
|
EP9450-1
EP9450-2
EP9450-3
EP9450-4
EP9450-5
EP9450-6
EP9450-7
EP9450-8
EP9450-9
EP9450-10
EP9450-6
EP9450-7
EP9450-8
EP9450-9
EP9450-1
EP9450-10
EP9450-15
EP9450-2
EP9450-3
EP9450-4
|
Untitled
Abstract: No abstract text available
Text: 3D7444 MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE SERIES 3D7444 FEATURES • • • • • • • • • • • PACKAGES Four indep’t programmable lines on a single chip All-silicon CMOS technology Low quiescent current (1mA typical) Leading- and trailing-edge accuracy
|
Original
|
PDF
|
3D7444
3D7444)
0C-70C)
|
variable ramp generator
Abstract: Knock AD9501 AD9501JN AD9501JP AD9501JQ AD9501SQ digital delay generator
Text: a FEATURES Single +5 V Supply TTL and CMOS Compatible 10 ps Delay Resolution 2.5 ns to 10 s Full-Scale Range Maximum Trigger Rate 50 MHz MIL-STD-883-Compliant Versions Available Digitally Programmable Delay Generator AD9501 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS
|
Original
|
PDF
|
MIL-STD-883-Compliant
AD9501
AD9501
C1295a
variable ramp generator
Knock
AD9501JN
AD9501JP
AD9501JQ
AD9501SQ
digital delay generator
|
Untitled
Abstract: No abstract text available
Text: SY89538L 3.3V Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay General Description The SY89538L integrated programmable clock synthesizer and fanout is part of a precision PLLbased clock generation family optimized for
|
Original
|
PDF
|
SY89538L
SY89538L
750MHz
M9999-092905-A
|
Untitled
Abstract: No abstract text available
Text: SY89538L 3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay General Description The SY89538L integrated programmable clock synthesizer and fanout is part of a precision PLLbased clock generation family optimized for
|
Original
|
PDF
|
SY89538L
SY89538L
750MHz
M9999-010808-E
|
Untitled
Abstract: No abstract text available
Text: ECL100K COMPATIBLE 8-BIT BINARY/ DECADE PROGRAMMABLE LOGIC DELAY LINE # ECL 100K input and output levels # Delays stable and precise The Logic Delay Lines are digitally programmable by the presence of either a " 1 " or a " 0 " at each of the programming #
|
OCR Scan
|
PDF
|
ECL100K
34-pin
132ns
|
Untitled
Abstract: No abstract text available
Text: DALLAS SEMICONDUCTOR DS1045 4-Bit Dual Programmable Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay • Two programmable outputs from a single input pro duce output-to-output delays between 9 and 84 ns depending on device type • Programmable via four input pins
|
OCR Scan
|
PDF
|
DS1045
16-pin
2bl413Q
|
CXB1159Q
Abstract: kf000
Text: SONY C X B 1 1 5 9 Q - Y High-Speed Programmable Delay Line/Duty Cycle Controller Description The CXB1159Q-V is an ultra high-speed Programmable Delay Line/Duty Cycle Controller IC. Two types of delay length settings are provided, coarse rough step length and tine (detailed step
|
OCR Scan
|
PDF
|
CXB1159Q-V
160ps
CXB11
CXB1159Q
kf000
|
Untitled
Abstract: No abstract text available
Text: lewprofilt 3-BIT PROGRAMMABLE ANALOG DELAY LINE Analog input and output All delays digitally programmable Delays stable and precise 14-pin DIP package .2 4 0 high Available in delays up to 36ns Available in 10 delay steps with resolution modules are o f hybrid co nstruction utilizing the proven
|
OCR Scan
|
PDF
|
14-pin
MIL-HDBK-21
|
Untitled
Abstract: No abstract text available
Text: COM’L AmPAL18P8B/AL/A/L Advanced Micro Devices 20-Pin Combinatorial TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • As fast as 15 ns maximum propagation delay ■ Universal combinatorial architecture ■ Programmable output polarity ■ Programmable replacement for high-speed
|
OCR Scan
|
PDF
|
AmPAL18P8B/AL/A/L
20-Pin
AmPAL18P8
KS000010-PAL
2350-019A
2984-006A
|