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    QUAD TWO INPUT NAND SCHMITT TRIGGER LOW POWER Search Results

    QUAD TWO INPUT NAND SCHMITT TRIGGER LOW POWER Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MHM411-21 Murata Manufacturing Co Ltd Ionizer Module, 100-120VAC-input, Negative Ion Visit Murata Manufacturing Co Ltd
    MGN1S1208MC-R7 Murata Manufacturing Co Ltd DC-DC 1W SM 12-8V GAN Visit Murata Manufacturing Co Ltd
    MGN1D120603MC-R7 Murata Manufacturing Co Ltd DC-DC 1W SM 12-6/-3V GAN Visit Murata Manufacturing Co Ltd
    MGN1S1212MC-R7 Murata Manufacturing Co Ltd DC-DC 1W SM 12-12V GAN Visit Murata Manufacturing Co Ltd
    MGN1S0508MC-R7 Murata Manufacturing Co Ltd DC-DC 1W SM 5-8V GAN Visit Murata Manufacturing Co Ltd

    QUAD TWO INPUT NAND SCHMITT TRIGGER LOW POWER Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    HD74LV132A

    Abstract: HD74LV132AFPEL HD74LV132ARPEL HD74LV132ATELL
    Text: HD74LV132A Quad. 2-input NAND Schmitt-triggers REJ03D0317–0300Z Previous ADE-205-260A (Z Rev.3.00 Jun. 03, 2004 Description The HD74LV132A has four two-input schmitt trigger NAND gates in a 14-pin package. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the


    Original     		HD74LV132A REJ03D0317 0300Z ADE-205-260A HD74LV132A 14-pin HD74LV132AFPEL HD74LV132ARPEL HD74LV132ATELL PDF

    74HC132

    Abstract: 74VHC132 74VHC132M 74VHC132MTC 74VHC132MTCX 74VHC132MX 74VHC132SJ M14A VHC00 VHC132
    Text: 74VHC132 Quad 2-Input NAND Schmitt Trigger tm Features General Description • High Speed: tPD = 3.9ns Typ. at VCC = 5V ■ Power down protection is provided on all inputs The VHC132 is an advanced high speed CMOS 2-input NAND Schmitt Trigger Gate fabricated with silicon gate


    Original     		74VHC132 VHC132 VHC00 74VHC132 74HC132 74VHC132M 74VHC132MTC 74VHC132MTCX 74VHC132MX 74VHC132SJ M14A PDF

    Untitled

    Abstract: No abstract text available
    Text: 74VHC132 Quad 2-Input NAND Schmitt Trigger Features General Description • High Speed: tPD = 3.9ns Typ. at VCC = 5V ■ Power down protection is provided on all inputs The VHC132 is an advanced high speed CMOS 2-input NAND Schmitt Trigger Gate fabricated with silicon gate


    Original     		74VHC132 VHC132 VHC00 74VHC132 PDF

    TTL Schmitt-Trigger LOW POWER SCHOTTKY

    Abstract: 74HC132 74VHC132 74VHC132M 74VHC132MTC 74VHC132SJ M14A M14D MTC14 VHC00
    Text: 74VHC132 Quad 2-Input NAND Schmitt Trigger Features General Description • High Speed: tPD = 3.9ns Typ. at VCC = 5V ■ Power down protection is provided on all inputs The VHC132 is an advanced high speed CMOS 2-input NAND Schmitt Trigger Gate fabricated with silicon gate


    Original     		74VHC132 VHC132 VHC00 74VHC132 TTL Schmitt-Trigger LOW POWER SCHOTTKY 74HC132 74VHC132M 74VHC132MTC 74VHC132SJ M14A M14D MTC14 PDF

    74LVC132A

    Abstract: 74LVC132ABQ 74LVC132AD 74LVC132APW TSSOP14
    Text: 74LVC132A Quad 2-input NAND Schmitt trigger Rev. 01 — 15 December 2006 Product data sheet 1. General description The 74LVC132A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is


    Original     		74LVC132A 74LVC132A 74LVC132ABQ 74LVC132AD 74LVC132APW TSSOP14 PDF

    MC14093BCP circuit diagram

    Abstract: cd4093 MC14093BCP CD4093 applications schematic MC14093B cd4093 electrical diagram CD4093 ic 10 pin diagram CD4093 applications
    Text: MC14093B Quad 2-Input NAND" Schmitt Trigger The MC14093B Schmitt trigger is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. These devices find primary use where low power dissipation and/or high noise immunity is desired. The MC14093B


    Original     		MC14093B MC14011B 14093B MC14093BCP 948G-01 MC14093BDTEL 948G-01 MC14093BDTR2 MC14093BCP circuit diagram cd4093 CD4093 applications schematic cd4093 electrical diagram CD4093 ic 10 pin diagram CD4093 applications PDF

    3 to 8 bit decoder vhdl IEEE format

    Abstract: ATL60 ATLS60 PO61 ttl buffer
    Text: ATL60 Features x x x x x x x x 0.6Pm Drawn Gate Length 0.5Pm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and Manage Chip-to-Chip Clock Skew


    Original     		ATL60 ATL60 3 to 8 bit decoder vhdl IEEE format ATLS60 PO61 ttl buffer PDF

    Tri-State Buffer CMOS

    Abstract: PTS41 books schmitt trigger cmos buffer 8x buffer cmos ATL60 ATLS60 mux8n AOI222
    Text: ATL60 Features • • • • • • • • 0.6µm Drawn Gate Length 0.5µm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to


    Original     		ATL60 ATL60 Tri-State Buffer CMOS PTS41 books schmitt trigger cmos buffer 8x buffer cmos ATLS60 mux8n AOI222 PDF

    TTL Schmitt-Trigger Inverters

    Abstract: Structure of D flip-flop DFFSR Tri-State Buffer CMOS TTL 3 input or gate ttl buffer TTL nand 3 input or gate 3 input Decoders actel PLL schematic AOI222
    Text: ATL60 Features • • • • • • • • 0.6µm Drawn Gate Length 0.5µm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to


    Original     		ATL60 ATL60 TTL Schmitt-Trigger Inverters Structure of D flip-flop DFFSR Tri-State Buffer CMOS TTL 3 input or gate ttl buffer TTL nand 3 input or gate 3 input Decoders actel PLL schematic AOI222 PDF

    PTS41

    Abstract: CMOS GATE ARRAY buf8
    Text: ATL60 Features • O.tHim Drawn Gate Length O.Stim Left Sea-of-Gates Architecture With Triple Level Metal • 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages • On Chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and Manage Chlp-to-Chip Clock Skew


    OCR Scan     		ATL60 ATL60 PTS41 CMOS GATE ARRAY buf8 PDF

    PO61

    Abstract: ATMEL 340 atmel 424 ATLS60 ATL60 ttl buffer 3.6v Tri-State Buffer bga ambit inverter circuit AOI222 ATMEL 218
    Text: Features • • • • • • • • 0.6 µm Drawn Gate Length 0.5 µm Leff Sea-of-Gates Architecture with Triple Level Metal 5.0V, 3.3V and 2.0V Operation including Mixed Voltages On-chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and


    Original     		ATL60 0388C 11/99/xM PO61 ATMEL 340 atmel 424 ATLS60 ttl buffer 3.6v Tri-State Buffer bga ambit inverter circuit AOI222 ATMEL 218 PDF

    Structure of D flip-flop DFFSR

    Abstract: AOI222 INV4 OAI23 atmel 424 MUX CMOS 0753B 5-input NAND Gates pic single phase inverter OAI22
    Text: ATL50 Features • • • • • • • • 0.5µm Drawn Gate Length 0.45µm Leff Sea-of-Gates Architecture With Triple Level Metal 3.3 Volt Operation 5.0 Volt compatible input buffers On-Chip Phase Locked Loop (PLL) Available to Synthesize Frequencies up to


    Original     		ATL50 ATL50 Structure of D flip-flop DFFSR AOI222 INV4 OAI23 atmel 424 MUX CMOS 0753B 5-input NAND Gates pic single phase inverter OAI22 PDF

    HEF4093BP

    Abstract: HEF4093BP datasheet free download HEF4093BT HEF4093B MO-001
    Text: HEF4093B Quad 2-input NAND Schmitt trigger Rev. 05 — 28 July 2009 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The


    Original     		HEF4093B HEF4093B HEF4093BP HEF4093BP datasheet free download HEF4093BT MO-001 PDF

    HEF4093BP

    Abstract: HEF4093BP datasheet free download 001aag104 HEF4093B HEF4093BT MO-001
    Text: HEF4093B Quad 2-input NAND Schmitt trigger Rev. 06 — 2 December 2009 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The


    Original     		HEF4093B HEF4093B HEF4093BP HEF4093BP datasheet free download 001aag104 HEF4093BT MO-001 PDF

    atmel 952

    Abstract: atmel h 952 ATL35 vhdl code for flip-flop jk flip flop to d flip flop conversion RTL 204 605 vhdl code for D Flipflop dssb oak dsp AOI222
    Text: Features • High Speed - 150 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 3.7 Million Used Gates and 976 Pins • System Level Integration Technology ™ ARM7TDMI and AVR RISC Microcontrollers, OakDSP™ and Lode™DSP Cores, 10T/100 Ethernet MAC, USB and PCI Cores,


    Original     		10T/100 ATL35 atmel 952 atmel h 952 vhdl code for flip-flop jk flip flop to d flip flop conversion RTL 204 605 vhdl code for D Flipflop dssb oak dsp AOI222 PDF

    HEF4093BP

    Abstract: HEF4093BP free HEF4093BT aSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER IN HEF4093BP datasheet free download HEF4093B MO-001 HEF4093 HEF40 Multivibrators
    Text: HEF4093B Quad 2-input NAND Schmitt trigger Rev. 7 — 1 September 2010 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The


    Original     		HEF4093B HEF4093B HEF4093BP HEF4093BP free HEF4093BT aSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER IN HEF4093BP datasheet free download MO-001 HEF4093 HEF40 Multivibrators PDF

    Untitled

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS DATA SHEET 74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger Product specification File under Integrated Circuits, IC06 1999 May 31 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger FEATURES • ESD protection:


    Original     		74AHC132; 74AHCT132 EIA/JESD22-A114-A EIA/JESD22-A115-A 74AHC/AHCT132 245002/01/pp16 PDF

    Untitled

    Abstract: No abstract text available
    Text: HEF4093B-Q100 Quad 2-input NAND Schmitt trigger Rev. 1 — 12 July 2012 Product data sheet 1. General description The HEF4093B-Q100 is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals.


    Original     		HEF4093B-Q100 HEF4093B-Q100 PDF

    Untitled

    Abstract: No abstract text available
    Text: ATL60 Features • • • • • • • • 0.6|.im D raw n G ate Length 0.5|im Left S e a -o f-G a te s A rch ite c tu re W ith T rip le Level M etal 5.0 V o lt, 3.3 V o lt, and 2.0 V o lt O p e ra tio n In c lu d in g M ixed V o lta g e s On C h ip P h ase Locked Loop A v a ila b le to S y n th e s ize F req u en cies up to


    OCR Scan     		ATL60 ATL60 PDF

    Untitled

    Abstract: No abstract text available
    Text: HEF4093B-Q100 Quad 2-input NAND Schmitt trigger Rev. 1 — 12 July 2012 Product data sheet 1. General description The HEF4093B-Q100 is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals.


    Original     		HEF4093B-Q100 HEF4093B-Q100 PDF

    Untitled

    Abstract: No abstract text available
    Text: HEF4093B Quad 2-input NAND Schmitt trigger Rev. 8 — 21 November 2011 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The


    Original     		HEF4093B HEF4093B PDF

    hef4093b

    Abstract: schmitt trigger application sheet HEF4093BC HEF4093BP
    Text: HEF4093B Quad 2-input NAND Schmitt trigger Rev. 8 — 21 November 2011 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The


    Original     		HEF4093B HEF4093B schmitt trigger application sheet HEF4093BC HEF4093BP PDF

    atmel 424

    Abstract: AMBIT inverter atmel 545 ATMEL 340 crystal oscillator buffer Structure of D flip-flop DFFSR s051 crystal OAI222 CMOS Transmission gate Specifications Tri-State Buffer CMOS
    Text: Features • 0.5 µm Drawn Gate Length 0.45µm Leff Sea-of-Gates Architecture With Triple Level Metal • 3.3V Operation • 5.0V Compatible Input Buffers • On-chip Phase Locked Loop (PLL) Available to Synthesize Frequencies up to 150 MHz • • • •


    Original     		ATL50 0753B 11/99/xM atmel 424 AMBIT inverter atmel 545 ATMEL 340 crystal oscillator buffer Structure of D flip-flop DFFSR s051 crystal OAI222 CMOS Transmission gate Specifications Tri-State Buffer CMOS PDF

    BLD Schmitt-trigger

    Abstract: 74AHC132 74AHC132D 74AHC132PW 74AHCT132 74AHCT132D 74AHCT132PW
    Text: INTEGRATED CIRCUITS DATA SHEET 74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger Product specification Supersedes data of 1999 May 31 File under Integrated Circuits, IC06 1999 Sep 24 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger


    Original     		74AHC132; 74AHCT132 EIA/JESD22-A114-A EIA/JESD22-A115-A EIA/JESD22-C101 245002/02/pp16 BLD Schmitt-trigger 74AHC132 74AHC132D 74AHC132PW 74AHCT132 74AHCT132D 74AHCT132PW PDF