AS4LC4M4E1-60JC
Abstract: AS4LC4M4E0-50JC AS4LC4M4E0-50JI AS4LC4M4E0-50TC AS4LC4M4E0-50TI AS4LC4M4E0-60JC AS4LC4M4E0-60JI
Text: March 2001 AS4LC4M4E0 AS4LC4M4E1 4Mx4 CMOS DRAM EDO Family Features • Refresh - 4096 refresh cycles, 64 ms refresh interval for AS4LC4M4E0 - 2048 refresh cycles, 32 ms refresh interval for AS4LC4M4E1 - RAS-only or CAS-before-RAS refresh or self-refresh
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Original
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24/26-pin
NC/A11
AS4LC4M4E1-60JC
AS4LC4M4E0-50JC
AS4LC4M4E0-50JI
AS4LC4M4E0-50TC
AS4LC4M4E0-50TI
AS4LC4M4E0-60JC
AS4LC4M4E0-60JI
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PDF
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Untitled
Abstract: No abstract text available
Text: February 2001 Advance Information AS4LC4M4E0 AS4LC4M4E1 4Mx4 CMOS DRAM EDO Family Features • Refresh - 4096 refresh cycles, 64 ms refresh interval for AS4LC4M4E0 - 2048 refresh cycles, 32 ms refresh interval for AS4LC4M4E1 - RAS-only or CAS-before-RAS refresh or self-refresh
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Original
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24/26-pin
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PDF
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Untitled
Abstract: No abstract text available
Text: $67&589.49 3 89#589.ð49#&026#'5$0#+IDVW#SDJH#PRGH, )HDWXUHV • Refresh • Organization: 262,144 words by 16 bits • High speed - 512 refresh cycles, 8 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh - Self-refresh option is available for new generation device
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Original
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AS4C256K16F0-50)
40-pin
40/44-pin
I/O15
AS4C256K16F0-50TC
AS4C256K16F0-25JC
AS4C256K16F0-30JC
AS4C256K16F0-35JC
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PDF
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AS4LC4M4E1-60JC
Abstract: AS4LC4M4E1-50JC AS4LC4M4E1-50JI AS4LC4M4E1-50TC AS4LC4M4E1-50TI AS4LC4M4E1-60JI AS4LC4M4E1-60TC AS4LC4M4E1-60TI
Text: April 2001 AS4LC4M4E1 4Mx4 CMOS DRAM EDO 3.3V Family Features • Refresh - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh • TTL-compatible, three-state I/O • JEDEC standard package - 300 mil, 24/26-pin SOJ
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Original
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24/26-pin
AS4LC4M4E1-60JC
AS4LC4M4E1-50JC
AS4LC4M4E1-50JI
AS4LC4M4E1-50TC
AS4LC4M4E1-50TI
AS4LC4M4E1-60JI
AS4LC4M4E1-60TC
AS4LC4M4E1-60TI
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PDF
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Untitled
Abstract: No abstract text available
Text: May 2001 AS4LC4M4E1 4Mx4 CMOS DRAM EDO 3.3V Family Features • Refresh - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh • TTL-compatible, three-state I/O • JEDEC standard package - 300 mil, 24/26-pin SOJ
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Original
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24/26-pin
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PDF
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AS4LC4M4F1-50JC
Abstract: AS4LC4M4F1-50JI AS4LC4M4F1-50TC AS4LC4M4F1-50TI AS4LC4M4F1-60JC AS4LC4M4F1-60JI AS4LC4M4F1-60TC
Text: May 2001 AS4LC4M4F1 4Mx4 CMOS DRAM Fast Page 3.3V Family Features • Refresh • Organization: 4,194,304 words × 4 bits • High speed - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh - 50/60 ns RAS access time
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Original
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24/26-pin
AS4LC4M4F1-50JC
AS4LC4M4F1-50JI
AS4LC4M4F1-50TC
AS4LC4M4F1-50TI
AS4LC4M4F1-60JC
AS4LC4M4F1-60JI
AS4LC4M4F1-60TC
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PDF
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Untitled
Abstract: No abstract text available
Text: AS4C256K16E0 5V 256Kx 16 CMOS DRAM EDO Features • Refresh - 5 1 2 refresh cycles, 8 m s refresh interval - RAS-only o r CAS-before-RAS refresh o r self-refresh - Self-refresh o p tio n is available for n e w g en eratio n device • O rganization: 2 6 2 ,1 4 4 w o rd s x 16 bits
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OCR Scan
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AS4C256K16E0
256Kx
AS4C256K16E0-25)
S4C256K16E0-30JC
S4C256K16E0-35JC
AS4C256K16E0-50JC
S4C256K16E0-50TC
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PDF
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Untitled
Abstract: No abstract text available
Text: $XJXVW $6&0 4 0 [ &026 4XDG&$6 '5$0 ('2 IDPLO\ HDWXUHV • Refresh - 2048 refresh cycles, 32 ms refresh interval for AS4C4M4E1Q - RAS-only and hidden refresh or CAS-before-RAS refresh TTL-compatible • 4 separate CAS pins allow for separate I/O operation
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Original
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28-pin
28-pin
AS4C4M4E1Q-50JC
AS4C4M4E1Q-60JC
AS4C4M4E1Q-50TC
AS4C4M4E1Q-60TC
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PDF
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HM62V8512LFP
Abstract: HM53861J M51419 16M dram dram zip 256kx16 m514280 hn27c1024hg 4M DRAM EDO M5241605 HM534253BT
Text: Memories Dynamic RAMs DRAM Access time ns 60 80 {HM5116100AS/ATS J F.P. 4k refresh -4Mx4 - {HM5116400AS/ATS ] F.P. 4k refresh 1HM51W16400AS/ATS ] F.P. 4k refresh 1HM5117400AS/ATS ] F.P. 2k refresh -3.3V operation- 16M- 70 -16Mx1 -3.3V operation— 2Mx8 -3.3V operation-
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OCR Scan
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-16Mx1
operation60
HM5116100AS/ATS
HM5116400AS/ATS
1HM51W16400AS/ATS
1HM5117400AS/ATS
HM51W17400ATS
HM5117800BJ/BTT
HM5117805BJ/BTT
HM51W17800BJ/BTT
HM62V8512LFP
HM53861J
M51419
16M dram
dram zip 256kx16
m514280
hn27c1024hg
4M DRAM EDO
M5241605
HM534253BT
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PDF
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Untitled
Abstract: No abstract text available
Text: January 2001 Advance Information AS4VC256K16EO 2.5V 256K X 16 CMOS DRAM EDO Features • EDO page mode • 512 refresh cycles, 8 ms refresh interval • Organization: 262,144 words x 16 bits • High speed - RAS-only or CAS-before-RAS refresh or self refresh
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Original
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AS4VC256K16EO
40-pin
40/44-pin
I/O15
AS4VC256K16E0-45JC
AS4VC256K16EO-45TC
AS4VC256K16EO-60JC
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PDF
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dp84300
Abstract: DP84300N dp84432 DP8418
Text: DP84300 PRELIMINARY National dOASemiconductor DP84300 Programmable Refresh Timer General Description Features The DP84300 programmable refresh timer ¡s a logic device which produces the desired refresh clock required by all dynamic memory systems. • One chip solution to produce RFCK timing for the
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OCR Scan
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DP84300
DP84300
DP8408A,
DP8409A,
DP8417,
DP8418,
DP8419,
DP8428,
DP8429
DP84300N
dp84432
DP8418
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PDF
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RR 113001
Abstract: 1M16E5
Text: Advance information •■ AS4VC1M16E5 A 2.5V lM x 16 CMOS lntelliwatt,v DRAM EDO Features 1 1024 refresh cycles, 16 ms refresh interval • Organization: 1,048,576 words x 16 bits • High speed - RAS-only or CAS-before-RAS refresh or self refresh 1Read-modify-write
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OCR Scan
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AS4VC1M16E5
42-pin
44/50-pin
AS4VC1M16E5-100JC
AS4VC1M16E5-100TC
1M16E5
RR 113001
1M16E5
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PDF
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AS4LC256K16EO
Abstract: No abstract text available
Text: AS4LC256K16EO 3.3V 256K X 16 CMOS DRAM EDO Features • 5V I/O tolerant • 512 refresh cycles, 8 ms refresh interval • Organization: 262,144 words x 16 bits • High speed - RAS-only or CAS-before-RAS refresh or self refresh - 45/50/60 ns RAS access time
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Original
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AS4LC256K16EO
40-pin
AS4LC256K16EO-45)
40/44-pin
I/O15
40-pin
AS4LC256K16E0-45JC
AS4LC256K16E0-50JC
AS4LC256K16EO
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PDF
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6E025
Abstract: No abstract text available
Text: Features • Refresh • O rganization: 262,144 w o rd s x 16 bits - 512 refresh cycles, 8 ms refresh interval • H ig h speed - 2 5 / 3 0 / 3 5 / 5 0 ns R A S access tim e - RA S-only o r CAS-before-RAS refresh o r self-refresh - 1 2 /1 6 /1 8 /2 5 ns co lu m n address access tim e
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OCR Scan
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40-pin
40/44-pin
6E0-25JC
S4C256K
16E0-30JC
256K1
6E0-35JC
16E0-50JC
6E025
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PDF
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|
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Untitled
Abstract: No abstract text available
Text: Advance information •■ AS4VC256K16E0 A 2.5V 256KX 16 CMOS DRAM EDO Features • 512 refresh cycles, 8 ms refresh interval • Organization: 262,144 w ords x 16 bits - RAS-only or CAS-before-RAS refresh or self refresh • H ig h speed - 45/60 ns KAS access tim e
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OCR Scan
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AS4VC256K16E0
256KX
40-pin
40/44-pin
40-pin
AS4VC256K16E0-45JC
AS4VC256K16E0-60JC
40/44-pin
AS4VC256K16E0-45TC
AS4VC256K16E0-60TC
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PDF
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13001 LZ
Abstract: SR 13001 PA 13001
Text: Advance information •■ II AS4VC1M16E5 2.5V 1Mx 16 CMOS lntelliwatt,v DRAM EDO Features • Organization: 1 ,0 4 8 ,5 7 6 w ords • H igh speed X • 10 24 refresh cycles, 16 m s refresh interval 16 bits - RAS-only or CAS-before-RAS refresh or self refresh
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OCR Scan
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AS4VC1M16E5
42-pin
44/50-pin
AS4VC1M16E5-50JC
AS4VC1M16E5-50TC
AS4VC1M16E5-60JC
AS4VC1M16E5-60TC
13001 LZ
SR 13001
PA 13001
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PDF
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WE VQE 23 F
Abstract: AM2970 Dynamic Memory Refresh Controller WE VQE 11 E WE VQE 24 E hat 901 cs dmc ge AM2968
Text: 1 . r ,/ Am2970 Dynamic Memory Timing Controller ^T'f v o 1A '-* ' A , PRELIMINARY > 3 to DISTINCTIVE CHARACTERISTICS Internal or external control of refresh Burst up to 512-cycle , distributed, or hidden refresh Memory access/refresh request arbitration
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OCR Scan
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Am2970
64K/256K
Am2968
512-cycle)
Am2970
AIS-B-15M-02/86-0
WE VQE 23 F
Dynamic Memory Refresh Controller
WE VQE 11 E
WE VQE 24 E
hat 901 cs
dmc ge
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PDF
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Untitled
Abstract: No abstract text available
Text: AS4LC256K16E0 A 3.3V 2 5 6 K X 16 CMOS DRAM EDO Features • 5 1 2 refresh cycles, 8 m s refresh interval - RAS-only or CAS-before-RAS refresh or self refresh • Organization: 262,144 w ords x 16 bits • H igh speed - 3 5 / 4 5 / 6 0 ns K K access tim e
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OCR Scan
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AS4LC256K16E0
AS4LC256K16E0-35)
40-pin
AS4LC256K16E0-35JC
AS4LC256K16E0-45JC
AS4LC256K16E0-60JC
40/44-pin
AS4LC256K16E0-35TC
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PDF
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AM2964B
Abstract: 16-32K
Text: Am2964B Advanced Micro Devices Dynamic Memory Controller DISTINCTIVE CHARACTERISTICS Dynamic Memory Controller for 16K and 64K MOS dynamic RAMs 8 -Bit Refresh Counter for refresh address generation, has clear input and terminal count output Refresh Counter terminal count selectable at 256 or 128
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OCR Scan
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Am2964B
WF001940
16-32K
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PDF
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Untitled
Abstract: No abstract text available
Text: $GYDQFHLQIRUPDWLRQ $66&0 90ð&026,QWHOOLZDWW'5$0 ('2 HDWXUHV • 1024 refresh cycles, 16 ms refresh interval • Organization: 1,048,576 words x 16 bits • High speed - RAS-only or CAS-before-RAS refresh or self refresh • Read-modify-write
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Original
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42-pin
44/50-pin
1DQ15
AS4SC1M16E5-100JC
AS4SC1M16E5-100TC
1M16E5
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PDF
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4LCIM16E5-50
Abstract: 4LCIM16E5 4LC1M16E5 AS4LC1M16ES j130007a 4C1M16E5-60 AS4CIM16E5 j13000
Text: Preliminary information Features • 1024 refresh cycles, 16 ms refresh interval • Organization: 1,048,576 w ords x 16 bits • High speed - RAS-only or CAS-before-RAS refresh • Read-modify-write • TTL-compatible, three-state DQ • JEDEC standard package and pinout
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OCR Scan
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42-pin
4C1M16E5)
50-pin
4LC1M16E5)
4C1M16E5-60)
4LC1M16E5-60)
AS4C1M16E5)
AS4LC1M16E5)
-60JC
16E5-50JC
4LCIM16E5-50
4LCIM16E5
4LC1M16E5
AS4LC1M16ES
j130007a
4C1M16E5-60
AS4CIM16E5
j13000
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PDF
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Untitled
Abstract: No abstract text available
Text: Il High Performance 256Kxl6 CMOS DRAM AS4C256K16F0 High Speed 256Kxl6 CMOS DRAM Fast Page Mode PRELIMINARY I F E A TU R E S_ • 512 refresh cycles, 8 ms refresh interval • Organization: 262,144 words by 16 bits - RAS-only or CAS-before-RAS refresh
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OCR Scan
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256Kxl6
AS4C256K16F0
256Kxl6
40-pin
4C256K16F0-50)
AS4C256K
16F0-50JC
40-pin
AS4C256K16F0-60JC
256K16
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PDF
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AS4C256K16F0-60JC
Abstract: ez 948 AS4C256K16F0 LRAL taa 723
Text: WÊ High Performance 256Kxl6 CMOS DRAM AS4C256K16F0 High Speed 256Kxl6 CMOS DRAM Fast Page Mode PRELIMINARY F E A TU R E S 512 refresh cycles, 8 ms refresh interval * Organization: 262,144 words by 16 bits - RAS-only or CAS-before-RAS refresh • High speed
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OCR Scan
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AS4C256K16F0
256Kxl6
256Kxl6
4C256K16F0-50)
I/014
I/013
I/012
40-pin
AS4C256KI6F0-50JC
AS4C256K16F0-60JC
AS4C256K16F0-60JC
ez 948
AS4C256K16F0
LRAL
taa 723
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PDF
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VG264265
Abstract: VG264260B
Text: VG264260BJ 262,144x16-Bit CMOS Dynamic RAM VIS TRUTH TABLE 2-CKE Notes: 1-4 CKEn-1 CKE n CURRENT STATE COMANDn ACTIONn L L Power-Down X Maintain Power-Down Self Refresh X Maintain Self Refresh Power-Down COMMAND INHIBIT or NOP Exit Power-Down 5 Self Refresh
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Original
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VG264260BJ
144x16-Bit
edg16
1G5-0157
VG264265
VG264260B
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PDF
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