AX1000
Abstract: n14132 SYNAPTICAD WAVEFORMER ax125c k7g4 diode AA16
Text: Advanced v1.1 Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • 350+ MHz System Performance 500+ MHZ Internal Performance High-Performance Embedded FIFOs 622Mb/s LVDS Capable I/Os S pe ci fi c at i on s • • • • • Up to 2 Million Equivalent System Gates
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622Mb/s
339kbits
AX1000
n14132
SYNAPTICAD WAVEFORMER
ax125c
k7g4
diode AA16
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dunlop s 708
Abstract: PTI 30 040 ga AX125 AX2000 CS180 FG256 FG324 FG484 PQ208 M33 thermal fuse
Text: Advanced v1.5 Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO"
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64-bit
608-bit
dunlop s 708
PTI 30 040 ga
AX125
AX2000
CS180
FG256
FG324
FG484
PQ208
M33 thermal fuse
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Axcelerator FPGAs
Abstract: AX125 AX2000 CQ208 CS180 PQ208 M33 thermal fuse AK 1022 Axcelerator Family FPGAs
Text: v2 .1 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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700Mb/s
295kbits
Axcelerator FPGAs
AX125
AX2000
CQ208
CS180
PQ208
M33 thermal fuse
AK 1022
Axcelerator Family FPGAs
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ACTEL CCGA 1152 mechanical
Abstract: AX125 AX2000 CQ208 CQ256 CS180 FG256 PQ208 Trd16 Axcelerator Family FPGAs
Text: v2.8 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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ACTEL CCGA 1152 mechanical
Abstract: lga 4x4 footprint AX125 AX2000 CQ208 CS180 FG256 PQ208 624-Pin tx 434
Text: v2.7 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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GCLR
Abstract: 676P Axcelerator Family FPGAs
Text: v2.4 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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AF4 din 74
Abstract: AF2.5 din 74 diode t25 4 g8 Axcelerator Family FPGAs
Text: v2.5 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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MA 6013
Abstract: No abstract text available
Text: v2.5 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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896-Pin
Abstract: smartpower IO290 Axcelerator Family FPGAs
Text: v2.2 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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AF367
Abstract: AK 1022 IC KA 2312 P2272 AX1000
Text: Advanced v1.6 Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • 350+ MHz System Performance 500+ MHZ Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os S pe ci fi c at i on s • • • • • Up to 2 Million Equivalent System Gates
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700Mb/s
295kbits
AF367
AK 1022
IC KA 2312
P2272
AX1000
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ACTEL CCGA 1152 mechanical
Abstract: ACTEL CCGA 624 mechanical L33 thermal fuse ACTEL CCGA 1152 pin configuration actel PLL schematic footprint cqfp 240 m20 thermal fuse 115 M33 thermal fuse AX125 AX2000
Text: v2.6 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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IO191
Abstract: Axcelerator Family FPGAs
Text: v2.3 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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b h21
Abstract: No abstract text available
Text: Revision 18 Axcelerator Family FPGAs Leading-Edge Performance • • • • 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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608-bit
b h21
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AX125
Abstract: AX2000 CQ208 CQ256 FG256 FG324 PQ208 AX2000-CQ256
Text: Revision 17 Axcelerator Family FPGAs Leading-Edge Performance • • • • 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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1510nm laser diode
Abstract: No abstract text available
Text: Data Sheet 2.5Gb/s Buried Het Laser non-WDM applications LC25WZ This laser module employs the Bookham strained layer MQW Buried Heterostructure DFB laser chip, and has been designed specifically for use in 2.5Gb/s long distance single channel optical fiber systems. The device is packaged in a
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LC25WZ
14-pin
175km
1510nm
TL9000
ISO9001
FM15040
ISO14001
EMS35100
BH13091
1510nm laser diode
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DP U1
Abstract: IO317 AX1000
Text: Advanced v1.5 Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)
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700Mb/s
339kbits
DP U1
IO317
AX1000
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LC25W
Abstract: LC25WZB 1510nm laser diode LC25Wz GR-468-CORE LC25WZCA-J28 laser diode submount
Text: Data Sheet 2.5Gb/s Buried Het Laser non-WDM applications LC25WZ This laser module employs the Bookham strained layer MQW Buried Heterostructure DFB laser chip, and has been designed specifically for use in 2.5Gb/s long distance single channel optical fiber systems. The device is packaged in a
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LC25WZ
14-pin
175km
1510nm
ISO14001
TL9000
ISO9001
FM15040
BH13091
LC25W
LC25WZB
1510nm laser diode
LC25Wz
GR-468-CORE
LC25WZCA-J28
laser diode submount
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AX1000
Abstract: No abstract text available
Text: Advanced v1.3 Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)
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64-bit
608-bit
14tains
AX1000
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v1493a
Abstract: AK 1022
Text: Advanced v1.4 Axcelerator Family FPGAs Leading-Edge Performance • • • • – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Registered I/Os with 64-bit Deep FIFO on Each Pin "PerPin FIFO" – Hot-Swap Compliant I/Os (Except PCI)
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700Mb/s
339kbits
v1493a
AK 1022
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RTAX2000
Abstract: rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3
Text: v5.1 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg
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TM1019
RTAX2000
rtax4000
CDB 455 C34
IO358
DIODE SMD V05
128X3
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CQ352-FPGA
Abstract: RTAX1000s-cq RTAX4000S RTAX2000 RTAX2000S-CQ352 FPGA Application Note schematic 324 CDB 455 C34 rtax4000 AP3433
Text: v4.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case
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TM1019
CQ352-FPGA
RTAX1000s-cq
RTAX4000S
RTAX2000
RTAX2000S-CQ352
FPGA Application Note
schematic 324
CDB 455 C34
rtax4000
AP3433
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RTAX2000
Abstract: RTAX2000S RTAX1000SL rtax250 RTAX250SL RTAX4000SL RTAX1000 RTAX-S RTAX1000S-SL rtax250s
Text: Rev ision 13 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)
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TM1019
MIL-STD-883B
Extended600
RTAX2000
RTAX2000S
RTAX1000SL
rtax250
RTAX250SL
RTAX4000SL
RTAX1000
RTAX-S
RTAX1000S-SL
rtax250s
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PC6070
Abstract: smj44c251 Video RAM 016 1144 SMJ44C250 44C25
Text: SMJ44C250 262 144 BY 4-BIT MULTIPORT VIDEO RAM SGMS037 — JANUARY 1991 Military Operating Temperature Range . . .-5 5 °C to 125°C JD Package^ Top View Dual Port Accessibility — Simultaneous and Asynchronous Access from the DRAM and SAM Ports 25 H S Ë
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OCR Scan
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SMJ44C250
SGMS037
28-pin
PC6070
smj44c251
Video RAM
016 1144
SMJ44C250
44C25
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PDF
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Untitled
Abstract: No abstract text available
Text: SMJ44C250 262 144 BY 4-BIT MULTIPORT VIDEO RAM SGMS037 — JANUARY 1991 * Military Operating Temperature Range JD Package* Top View . . , - 5 5 ° C t o 125°C DRAM: 262 144 Words SAM: 512 Words * * * x x 4 Bits 4 Bits 28 : 27 : 3 26 : SDQ2 TRG c 4 25 :
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OCR Scan
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SMJ44C250
SGMS037
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PDF
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