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    SN74LVC112A

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289D – JANUARY 1993 – REVISED JANUARY 1997 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V


    Original     		PDF SN74LVC112A SCAS289D MIL-STD-883, JESD-17 SN74LVC112A

    SN74LVC112A

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289D - JANUARY 1993 - REVISED JANUARY 1997 • • • • • • • EPIC Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V


    OCR Scan     		PDF SN74LVC112A SCAS289D MIL-STD-883, JESD-17 1til723 SN74LVC112A