Untitled
Abstract: No abstract text available
Text: SN54LV02, SN74LV02 QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS183B − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC Enhanced-Performance Implanted D D D D 1Y 1A 1B 2Y 2A 2B GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A SN54LV02 . . . FK PACKAGE
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SN54LV02,
SN74LV02
SCLS183B
MIL-STD-883C,
JESD-17
300-mil
SN54LV02
SN74LV02
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SN54LV02
Abstract: SN74LV02
Text: SN54LV02, SN74LV02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS183B – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)
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PDF
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SN54LV02,
SN74LV02
SCLS183B
MIL-STD-883C,
JESD-17
300-mil
SN54LV02
SN54LV02
SN74LV02
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Untitled
Abstract: No abstract text available
Text: SN54LV02, SN74LV02 QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS183B − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC Enhanced-Performance Implanted D D D D 1Y 1A 1B 2Y 2A 2B GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A SN54LV02 . . . FK PACKAGE
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Original
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PDF
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SN54LV02,
SN74LV02
SCLS183B
SN54LV02
MIL-STD-883C,
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Untitled
Abstract: No abstract text available
Text: SN54LV02, SN74LV02 QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS183B − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC Enhanced-Performance Implanted D D D D 1Y 1A 1B 2Y 2A 2B GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A SN54LV02 . . . FK PACKAGE
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Original
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PDF
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SN54LV02,
SN74LV02
SCLS183B
MIL-STD-883C,
JESD-17
300-mil
SN54LV02
SN74LV02
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SN54LV02
Abstract: SN74LV02 SN74LV02D SN74LV02DBLE SN74LV02DR SN74LV02PWLE
Text: SN54LV02, SN74LV02 QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS183B − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC Enhanced-Performance Implanted D D D D 1Y 1A 1B 2Y 2A 2B GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A SN54LV02 . . . FK PACKAGE
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Original
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PDF
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SN54LV02,
SN74LV02
SCLS183B
SN54LV02
MIL-STD-883C,
SN54LV02
SN74LV02
SN74LV02D
SN74LV02DBLE
SN74LV02DR
SN74LV02PWLE
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Untitled
Abstract: No abstract text available
Text: SN54LV02, SN74LV02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS183B – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)
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Original
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PDF
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SN54LV02,
SN74LV02
SCLS183B
MIL-STD-883C,
JESD-17
300-mil
SN54LV02
SN74LV02
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SN54LV02
Abstract: SN74LV02
Text: SN54LV02, SN74LV02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS183B – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)
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Original
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PDF
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SN54LV02,
SN74LV02
SCLS183B
MIL-STD-883C,
JESD-17
300-mil
SN54LV02
SN54LV02
SN74LV02
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SN74ALVCH162245
Abstract: Schottky Barrier Diode Bus-Termination Array SN7400 CLOCKED SLLS210 SCAD001D TEXAS INSTRUMENTS SN7400 SERIES buffer SN74LVCC4245 sn74154 SDAD001C SN7497
Text: Section 4 Logic Selection Guide ABT – Advanced BiCMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 ABTE/ETL – Advanced BiCMOS Technology/ Enhanced Transceiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
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SN74HC02 Spice model
Abstract: philips semiconductor data handbook SDAD001C SDFD001B SCAD001D SN7497 spice model SN74AHC14 spice Transistor Crossreference SLLS210 ci ttl sn74ls00
Text: LOGIC OVERVIEW 1 FUNCTIONAL INDEX 2 FUNCTIONAL CROSSĆREFERENCE 3 DEVICE SELECTION GUIDE 4 3 LOGIC SELECTION GUIDE FIRST QUARTER 1997 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest
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Untitled
Abstract: No abstract text available
Text: SN54LV02, SN74LV02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES S C L S 1 8 3 B - FEBRUARY 1 9 9 3 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vcc, Ta= 25°C Typical V q h v (Output Vqh Undershoot)
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OCR Scan
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PDF
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SN54LV02,
SN74LV02
MIL-STD-883C,
SN54LV02
SN74LV02
JESD-17
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D103D
Abstract: x1sv 199S SN74LV02
Text: SN74LV02 QUADRUPLE 2-INPUT POSITIVE-NOR GATE SCLS183A - FEBRUARY 1993 - REVISED JULY 1995 • EPIC Enhanced-Performance Implanted CMOS 2-n Process • Typical V q l p (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C • Typical Vq hv (Output Vq h Undershoot)
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OCR Scan
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PDF
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SN74LV02
SCLS183A
MIL-STD-883C,
JESD-17
D103D31
D103D
x1sv
199S
SN74LV02
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SN74LV02
Abstract: No abstract text available
Text: SN74LV02 QUADRUPLE 2-INPUT POSITIVE-NOR GATE S C LS183- FEBRUARY 1993-R E V IS E D MARCH 1994 D, DB, OR PW PACKAGE TOP VIEW • EPIC (Enhanced-Performance Implanted CMOS) 2-\i Process • Typical V q l p (Output Ground Bounce) < 0.8 V at Vcc = 3.3 V, TA = 25°C
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OCR Scan
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PDF
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SN74LV02
SCLS183-
1993-REVISED
MIL-STD-883C,
JESD-17
SCLS183
1bl723
SN74LV02
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