28F3202C3
Abstract: 29066
Text: PRODUCT PREVIEW 3 VOLT ADVANCED+ STACKED CHIP SCALE PACKAGE MEMORY 16-Mbit Flash + 2-Mbit SRAM - 28F1602C3 16-Mbit Flash + 4-Mbit SRAM - 28F1604C3 32-Mbit Flash + 4-Mbit SRAM - 28F3204C3 32-Mbit Flash + 2-Mbit SRAM - 28F3202C3 ! Flash Memory Plus SRAM
|
Original
|
16-Mbit
28F1602C3
32-Mbit
28F3204C3
28F1604C3
28F3202C3
16-Mb
32-Mb
28F3202C3
29066
|
PDF
|
TCAM
Abstract: nP3400 PB3450 nP3450 amcc np3400
Text: nP3450 Advanced Product Brief 4.4Gbps Integrated Network Processor and Traffic Manager PB3450 / V0.3 / 04/24/2003 • Switched Ethernet Platforms • Ethernet Over SONET/SDH • CPE Equipments, MTU/MDU SRAM SRAM SRAM SRAM/ TCAM Applications Features 24 FE
|
Original
|
nP3450
PB3450
nP3450
nP3400
nP3400
nP3400.
OC-192
TCAM
amcc np3400
|
PDF
|
tcam
Abstract: MPLS nP3450 NP3454 nP3400 amcc np3400 np3404
Text: nP3454 Advanced Product Brief PB3454 / V0.3 / 04/24/2003 4.4Gbps Integrated Network Processor and Traffic Manager SRAM SRAM SRAM SRAM/ TCAM Applications • Switched Ethernet Platforms • Ethernet Over SONET/SDH • CPE Equipments, MTU/MDU Features 2 GE nP3454
|
Original
|
nP3454
PB3454
nP3454
nP3404
nP3404
nP3404.
tcam
MPLS
nP3450
nP3400
amcc np3400
|
PDF
|
AG29
Abstract: ipug45_01.5 transistor w1d transistor w4B SRAM SAMSUNG FC1152 3ah22
Text: ispLever CORE TM QDRII+ SRAM Controller MACO Core User’s Guide June 2008 ipug45_01.5 QDRII+ SRAM Controller MACO Core User’s Guide Lattice Semiconductor Introduction Lattice’s QDRII and QDRII+ QDRII/II+ SRAM Controller MACO core assists the FPGA designer’s efforts by
|
Original
|
ipug45
AG29
ipug45_01.5
transistor w1d
transistor w4B
SRAM SAMSUNG
FC1152
3ah22
|
PDF
|
Untitled
Abstract: No abstract text available
Text: LatticeMico Asynchronous SRAM Controller The LatticeMico asynchronous SRAM controller is a slave device for the WISHBONE architecture. It interfaces to an industry-standard asynchronous SRAM device. Version This document describes the 3.2 version of the LatticeMico asynchronous
|
Original
|
32-bit
|
PDF
|
ISSI Signs SRAM Technology Licensing Agreement with IBM
Abstract: Licensing Agreement with IBM
Text: ISSI Signs SRAM Technology Licensing Agreement with IBM SAN JOSE, Calif., Feb. 27, 2012 - ISSI has signed a technology licensing agreement with IBM around SRAM technology, enhancing a relationship that started in 2004 for SRAM technology. Said Tom Reeves, VP of Business Development and Licensing, at IBM: "IBM has a rich and extensive IP portfolio in
|
Original
|
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Rev 2; 5/06 DS2045W 3.3V Single-Piece 1Mb Nonvolatile SRAM The DS2045W is a 1Mb reflowable nonvolatile NV SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in
|
Original
|
DS2045W
256-ball
DS2045W
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Rev 1; 5/06 DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM The DS2065W is a 8Mb reflowable nonvolatile NV SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in
|
Original
|
DS2065W
256-ball
DS2065W
|
PDF
|
DS2045AB
Abstract: DS2045AB-100 DS2045AB-70 DS2045Y DS2045Y-100 DS2045Y-70 DS80C390 DS2045
Text: Rev 0; 10/04 DS2045Y/AB Rechargeable 1M Nonvolatile SRAM Features The DS2045 is a 1Mb rechargeable nonvolatile NV SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in
|
Original
|
DS2045Y/AB
DS2045
256-ball
045Y/AB
DS2045AB
DS2045AB-100
DS2045AB-70
DS2045Y
DS2045Y-100
DS2045Y-70
DS80C390
|
PDF
|
DS1270W
Abstract: No abstract text available
Text: Rev 0; 8/06 3.3V Single-Piece 16Mb Nonvolatile SRAM Features The DS2070W is a 16Mb reflowable nonvolatile NV SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in
|
Original
|
DS2070W
256-ball
microA19
DS2070W
DS1270W
|
PDF
|
qdrii sram
Abstract: No abstract text available
Text: QDRII SRAM Controller MegaCore Function Errata Sheet December 2006, MegaCore Version 6.1 This document addresses known errata and documentation issues for the QDRII SRAM Controller MegaCore function version 6.1. Errata are functional defects or errors, which may cause the QDRII SRAM
|
Original
|
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Rev 2; 5/06 DS2045L 3.3V Single-Piece 1Mb Nonvolatile SRAM The DS2045L is a 1Mb reflowable nonvolatile NV SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in
|
Original
|
DS2045L
256-ball
DS2045L
|
PDF
|
DS1270W
Abstract: DS2070W-100 DS2070W
Text: Rev 0; 8/06 3.3V Single-Piece 16Mb Nonvolatile SRAM Features The DS2070W is a 16Mb reflowable nonvolatile NV SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in
|
Original
|
DS2070W
256-ball
DS2070W
DS1270W
DS2070W-100
|
PDF
|
ModelSim
Abstract: No abstract text available
Text: QDRII SRAM Controller MegaCore Function Errata Sheet June 2007, MegaCore Version 7.1 This document addresses known errata and documentation issues for the QDRII SRAM Controller MegaCore function version 7.1. Errata are functional defects or errors, which may cause the QDRII SRAM
|
Original
|
|
PDF
|
|
|
ic 4082 16 pins
Abstract: ic 4082 ic 4082 and pin configuration
Text: IP X fd t Integrated Ete1i'ice Technology, Inc. Inf7MBV4150 128K x 64/256K x 72 SYNC HR ON OUS PIPELINED BU RST SRAM 256K x 72 BU RST Z B T SRAM MODULE FAMILY IDT7MBV4151 IDT7MBV4152 FEATURES: DESCRIPTION: • Pin compatible module family for pipelined burst SRAM and
|
OCR Scan
|
64/256K
Inf7MBV4150
IDT7MBV4151
IDT7MBV4152
160-lead
66MHz,
IDT7MBV4150/51/52
BV4150
7MBV4151
ic 4082 16 pins
ic 4082
ic 4082 and pin configuration
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 8 Megabit Flash + 2 Megabit SRAM ComboMemory SST32LH802 Advance Inform ation FEATURES: • Organized as 512 K x16 Flash + 128Kx16 SRAM or 512K x8 x2 Flash + 128K x8 x2 SRAM • Single 3.0-3.6V Read and Write Operations • Concurrent Operation - Read from or write to SRAM while erase/
|
OCR Scan
|
SST32LH802
128Kx16
SST32LH802
|
PDF
|
jmicron
Abstract: MT58C1
Text: SSE D MICRON TECHNOLOGY INC IC R O N • b l l i s m 0005^53 LIT 16K X IPIRN MT58C1616 DIE 16 SYNCHRONOUS SRAM -T MILITARY SRAM DIE 16Kx 16 SRAM WITH CLOCKED, REGISTERED INPUTS FEATURES • • • • • • • • Fast access times: 20,25 and 35ns
|
OCR Scan
|
MT58C1616
jmicron
MT58C1
|
PDF
|
Untitled
Abstract: No abstract text available
Text: TOSHIBA TH50VSF1302/1303AAXB TOSHIBA MULTI CHIP INTEGRATED CIRCUIT TENTATIVE SILICON GATE CMOS SRAM AND FLASH MEMORY MIXED MULTI CHIP PACKAGE DESCRIPTION The TH50VSF1302/1303AAXB is a package of mixed 2,097,152-bit SRAM and 8,388,608-bit FLASH memory. The SRAM and FLASH memory organized 262,144 words by 8 bits SRAM and 1,048,576
|
OCR Scan
|
TH50VSF1302/1303AAXB
TH50VSF1302/1303AAXB
152-bit
608-bit
48-pin
|
PDF
|
Untitled
Abstract: No abstract text available
Text: TOSHIBA TH 50VSF1320/1321AAXB TENTATIVE TOSHIBA MULTI CHIP INTEGRATED CIRCUIT SILICON GATE CMOS SRAM AND FLASH MEMORY MIXED MULTI CHIP PACKAGE DESCRIPTION The TH50VSF1320/1321AAXB is a package of mixed 2,097,152-bit SRAM and 8,388,608-bit FLASH memory. The SRAM and FLASH memory organized 262,144 words by 8 bits SRAM and 1,048,576
|
OCR Scan
|
50VSF1320/1321AAXB
TH50VSF1320/1321AAXB
152-bit
608-bit
48-pin
TH50VSF1320/1321
|
PDF
|
Untitled
Abstract: No abstract text available
Text: MICRON TECHNOLOGY INC SSE ]> b i l l i g 0004GGS ¿OI MICRON 256K X IPIRN MT8S25632 32 SRAM MODULE - ' " P J t - i ' 5 - 1 4 SRAM MODULE 256K X 32 SRAM FEATURES • High speed: 15*, 20,25 and 35ns • High-density 1MB design • High-performance, low-power, CMOS double-metal
|
OCR Scan
|
0004GGS
MT8S25632
64-Pin
MT6S2S632
|
PDF
|
Untitled
Abstract: No abstract text available
Text: TOSHIBA TH 50VSF1 3 2 0 /1 3 2 1AAXB TENTATIVE TOSHIBA MULTI CHIP INTEGRATED CIRCUIT SILICON GATE CMOS SRAM AND FLASH MEMORY MIXED MULTI CHIP PACKAGE DESCRIPTION The TH50VSF1320/1321AAXB is a package of mixed 2,097,152-bit SRAM and 8,388,608-bit FLASH memory. The SRAM and FLASH memory organized 262,144 words by 8 bits SRAM and 1,048,576
|
OCR Scan
|
50VSF1
TH50VSF1320/1321AAXB
152-bit
608-bit
48-pin
TH50VSF1320/1321A
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Philips Semiconductors Preliminary specification 320 macroceil SRAM CPLD PZ3320C/PZ3320N FEATURES DESCRIPTION • 320 macrocell SRAM based CPLD The PZ3320 device is a member of the CoolRunner family of high-density SRAM-based CPLDs Complex Programmable Logic
|
OCR Scan
|
PZ3320C/PZ3320N
1-888-CoolPLD
PZ3320
|
PDF
|
MTSC1008
Abstract: micron sram DDD347D MT5C1008 MT5C1008DJ-25 5A143 MT5C100B IA15I 81A12
Text: MICRON TE C H N O L O G Y INC M I C R O t i l l 5 in Q 0 034b4 Oñb SSE » MT5C1008 128K X 8 SRAM N SRAM 128K x 8 SRAM 5 VOLT SRAM WITH OUTPUT ENABLE FEATURES • High speed: 12*, 15*, 17,20,25,35 and 45ns • High-performance, low-power, CMOS double-metal
|
OCR Scan
|
MT5C1008
G003M71
MTSC1008
micron sram
DDD347D
MT5C1008DJ-25
5A143
MT5C100B
IA15I
81A12
|
PDF
|
Untitled
Abstract: No abstract text available
Text: PRELIMINARY MT58LC64K32D9 64KX 32 SYNCBURST SRAM MICRON • lfcCHNOlOGY. INC. 64K x 32 SRAM + 3 .3 V S U P P L Y , P IP E L IN E D , S IN G L E -C Y C L E D ES ELEC T AND SELECTABLE BURST M O DE NEW SYNCHRONOUS SRAM FEATURES • • • • • • • •
|
OCR Scan
|
MT58LC64K32D9
|
PDF
|
