SRAM SPICE Search Results

SRAM SPICE Result Highlights (5)

Part	Manufacturer	Description
AM27LS07PC	Rochester Electronics LLC	27LS07 - Standard SRAM, 16X4
CY7C167A-35PC	Rochester Electronics LLC	CY7C167A - CMOS SRAM
HM3-6504B-9	Rochester Electronics LLC	HM3-6504 - Standard SRAM, 4KX1, 220ns, CMOS
HM4-6504B-9	Rochester Electronics LLC	HM4-6504 - Standard SRAM, 4KX1, 220ns, CMOS
MD2114A-5	Rochester Electronics LLC	2114A - 1K X 4 SRAM

SRAM SPICE Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
58LC32K Abstract: 58Lc32 Text: JÚl ft 8 19« ADVANCE MT58LC32K36C4 32K X 36 SYNCHRONOUS SRAM MICRON • SCMlCONOlATTOa MC SYNCHRONOUS SRAM 32K x 36 SRAM +3.3V SUPPLY, FULLY REGISTERED INPUTS AND OUTPUTS AND BURST COUNTER FEATURES • • • • • • • • • • • • • •	OCR Scan	MT58LC32K36C4 486/Pentiumâ MT58LC32K36C4LG-10 64-bit MT58LC32K36C4LG-7 ITTMLC32K36C4 C1993. 58LC32K 58Lc32	PDF
bsu 479 Abstract: atmel 912 asynchronous RAM atmel 0848 "32K x 32" SRAM 32K 4K x 8 Synchronous Dynamic RAM atmel 0529 Text: ATL25 Memory SRAMs - 1.1 - 08/00 Memory ATL25 0.25µ Compiled Gate Level SRAMs Compiled Gate Level SRAM Loading . 9-2 Common Single Port SRAM Sizes: Table. 9-2	Original	ATL25 PRAM48X4 bsu 479 atmel 912 asynchronous RAM atmel 0848 "32K x 32" SRAM 32K 4K x 8 Synchronous Dynamic RAM atmel 0529	PDF
static SRAM single port Abstract: al5b ATMEL 910 din 74 ATL35 PRAM12X32R1W1 Text: ATL35 Memory SRAMs-1.2-04/99 Memory ATL35 0.35µ Compiled Gate Level SRAMs Compiled Gate Level SRAM Loading . 9-2 Common Single Port SRAM Sizes: Table. 9-2	Original	ATL35 PRAM48X4 PRAM32x36R1W1) static SRAM single port al5b ATMEL 910 din 74 PRAM12X32R1W1	PDF
Untitled Abstract: No abstract text available Text: JUL 8 e 1993 ADVANCE MICRON • 32K celtico no üCTon Me SYNCHRONOUS SRAM MT58LC32K36B2 36 SYNCHRONOUS SRAM X 32K x 36 SRAM +3.3V SUPPLY WITH CLOCKED, REGISTERED INPUTS AND BURST COUNTER FEATURES • • • • • • • • • • • • • • Fast access times: 9,10,12 and 17ns	OCR Scan	MT58LC32K36B2 486/Pentiumâ 100-lead MT58LC32K36B2LG-12 64-bit MT58LC32K36B2LG-9 MT56LC32K3662 C1993.	PDF
FKC2 Abstract: No abstract text available Text: ADVANCE M I lf P f lM MT58LC32K36A6 32 K x 36 SYNCHRONOUS SRAM SYNCHRONOUS SRAM 32K x 36 SRAM +3.3V SUPPLY, FULLY REGISTERED I/O AND LINEAR BURST COUNTER FEATURES • • • • • • • • • • • • • • • Fast access times: 7 ,1 0 ,1 2 and 15ns	OCR Scan	MT58LC32K36A6 100-lead 32-bit 680X0 MT58LC32K36A6LG-10 64-bit MT58LC32K36A6LG-7 FKC2	PDF
Untitled Abstract: No abstract text available Text: -¿UL %e ?9£3 ADVANCE MICRON I 32K KM'CONOUCTOR. MC SYNCHRONOUS SRAM X MT58LC32K36A6 36 SYNCHRONOUS SRAM 32K x 36 SRAM +3.3V SUPPLY, FULLY REGISTERED I/O AND LINEAR BURST COUNTER FEATURES • • • • • • • • • • • • • • • Fast access times: 7 ,1 0 ,1 2 and 15ns	OCR Scan	MT58LC32K36A6 680X0 MT58LC32K36A6LG-10 64-bit MT58LC32K36A6LG-7 MTSSLC32K36A6	PDF
diagram power supply LG 32 lh 35 fr Abstract: No abstract text available Text: JUL 8 6 NW ADVANCE MT58LC32K36M1 32K X 36 SYNCHRONOUS SRAM MICRON • SfMlCOMOlKTTOR MC 32K x 36 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY WITH CLOCKED, REGISTERED INPUTS AND LINEAR BURST COUNTER FEATURES • • • • • • • • • • • • • • Fast access times: 9 ,1 0 ,1 2 and 17ns	OCR Scan	MT58LC32K36M1 100-lead 680X0 MT58LC32K36M1 LG-12 64-bit MTS8LC32K36M1 diagram power supply LG 32 lh 35 fr	PDF
AN1004 Abstract: CY7C1355V25-133AC AN1003 CY7C1360V25-200AC CY7C1361V25-133AC GS84036B-100 GVT71256B36B-8 GVT71256D36T-5 MT58L256L18PT-6 Text: AN1004 APPLICATION NOTE Cycle and Access Time Interpretation for Non-Technical People SRAM vendors often differ in the way they identify a particular speed of synchronous SRAM. Synchronous SRAM speeds are identified in one of two ways, cycle time or access time also known as clock to data/output valid . This can cause confusion for those that do not understand the	Original	AN1004 AN1004 CY7C1355V25-133AC AN1003 CY7C1360V25-200AC CY7C1361V25-133AC GS84036B-100 GVT71256B36B-8 GVT71256D36T-5 MT58L256L18PT-6	PDF
80486 microprocessor block diagram and pin diagrams Abstract: 1S1665 Text: ADVANCE iu i\|i“ n f n N K 1ll1— LTc MT58LC32K36M1 32K X 36 SYNCHRONOUS SRAM SYNCHRONOUS SRAM 32K x 36 SRAM +3.3V SUPPLY W ITH CLOCKED, REGISTERED INPUTS AND LINEAR BURST COUNTER FEATURES • • • • • • • • • • • • • • Fast access times: 9 ,1 0 ,1 2 and 17ns	OCR Scan	MT58LC32K36M1 100-lead 32-bit 680X0 MT58LC32K36M1LG-12 64-bit 80486 microprocessor block diagram and pin diagrams 1S1665	PDF
10256K Abstract: AMAA Text: 32K x 36 Synchronous SRAM +3.3 V Supply With Clocked, Registered Inputs and Burst Counter FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 9,10,12, and 17 ns The Shaip Synchronous SRAM family employs high speed, kjw-power CMOS designs using a thin-fllm tran	OCR Scan	486/PentiumTM 100-Lead 32-Bit Access/15 Access/20 LHS2V1036B2-12 64-BIT 52V1036B2-10 LH52V1036B2-9 10256K AMAA	PDF
Untitled Abstract: No abstract text available Text: PRELIMINARY 32K x 32 Pipelined Burst SRAM +3.3 V Supply, Fully Registered Inputs, Outputs, and Burst Counter FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 8 and 9 ns The Sharp Synchronous SRAM family employs high speed, low-power CMOS designs using a thin-film tran	OCR Scan	100-pin DES10. LH51V1032 LH51V1032C4 100TQFP TQFP-1OO-P-1420) LH51V1032C4	PDF
Untitled Abstract: No abstract text available Text: 32K x 36 Synchronous SRAM +3.3 V Supply, Fully Registered Inputs, Outputs, and Burst Counter FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 7 ,10,12, and 15 ns The Sharp Synchronous SRAM family employs high speed, law-pcMier CMOS designs using a thm-fflm tran	OCR Scan	486/PentiumTM 100-Lead 32-Bit 52V1036C4-10 LH52V1036-7 LH52V1036C4 LH52V1036C4 -----------------------------------32K LH52V1036G4-7 52V1036C4-11	PDF
FIFO36 Abstract: DWH-11 ISERDES ML561 mig ddr virtex XAPP853 iodelay CY7C1520JV18-300BZXC K7R643684M-FC30 DWL-11 Text: Application Note: Virtex-5 Family R XAPP853 v1.2 October 6, 2008 Summary QDR II SRAM Interface for Virtex-5 Devices Author: Lakshmi Gopalakrishnan This application note describes the implementation and timing details of a Quad Data Rate (QDR II) SRAM interface for Virtex -5 devices. The synthesizable reference design leverages	Original	XAPP853 36-bit FIFO36 DWH-11 ISERDES ML561 mig ddr virtex XAPP853 iodelay CY7C1520JV18-300BZXC K7R643684M-FC30 DWL-11	PDF
FIFO36 Abstract: K7R643684M-FC30 iodelay DWL-20 ML561 XAPP853 DWH-21 ISERDES BWH-01 Virtex-5 FPGA Text: Application Note: Virtex-5 Family R XAPP853 v1.3 June 7, 2010 Summary QDR II SRAM Interface for Virtex-5 Devices Author: Lakshmi Gopalakrishnan This application note describes the implementation and timing details of a Quad Data Rate (QDR II) SRAM interface for Virtex -5 devices. The synthesizable reference design leverages	Original	XAPP853 36-bit FIFO36 K7R643684M-FC30 iodelay DWL-20 ML561 XAPP853 DWH-21 ISERDES BWH-01 Virtex-5 FPGA	PDF

transistor GW 93 H Abstract: "32K x 32" SRAM Text: LH 5 1 V 1032 C 4 PRELIMINARY 32K X 32 Pipelined Burst SRAM +3.3 V Supply, Fully Registered Inputs, Outputs, and Burst Counter FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 8 and 9 ns The Sharp Synchronous SRAM family employs high speed, low-power CMOS designs using a thin^ilm tran	OCR Scan	LH51V1032C4 LH51V1032 LH51V103204 100TQFP TQFP-1OO-P-1420) 100-pin LH51V1032C4-15 transistor GW 93 H "32K x 32" SRAM	PDF
max 1786 Abstract: SRAM timing ATL60 Text: SRAMs-3.3-6/96 Memory ATL60 SRAMs Compiled Gate Level Compiled Gate Level SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Common Single Port SRAM Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2	Original	ATL60 DP32x36) max 1786 SRAM timing	PDF
ATL35 Abstract: No abstract text available Text: ATL35 Memory SRAMs-1.0-12/97 Memory ATL35 0.35µ Compiled Gate Level SRAMs Compiled Gate Level SRAMs . 9-2 Common Single Port SRAM Sizes: Table. 9-2	Original	ATL35 PRAM48X4 PRAM32x36R1W1)	PDF
ATL35 Abstract: sram spice ATMEL 744 Text: ATL35 Memory SRAMs-1.0-12/97 Memory ATL35 0.35µ Compiled Gate Level SRAMs Compiled Gate Level SRAMs . 9-2 Common Single Port SRAM Sizes: Table. 9-2	Original	ATL35 PRAM48X4 PRAM32x36R1W1) sram spice ATMEL 744	PDF
ATMEL 634 Abstract: MH1099 MH1242 PO11V5 dual lvds vhdl Text: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)	Original	5962-01B01 4138G ATMEL 634 MH1099 MH1242 PO11V5 dual lvds vhdl	PDF
Untitled Abstract: No abstract text available Text: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)	Original	5962-01B01 4138Gâ	PDF
MH1099 Abstract: MH1242 PO11V5 4138G Text: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)	Original	5962-01B01 4138G MH1099 MH1242 PO11V5	PDF
ATMEL 634 Abstract: ambit rev 4 LSI CMOS GATE ARRAY PO11V5 MH1099 MH1242 705uA Text: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TPRAM; Gate Level or Embedded	Original	5962-01B01 4138F ATMEL 634 ambit rev 4 LSI CMOS GATE ARRAY PO11V5 MH1099 MH1242 705uA	PDF
PO88 Abstract: ttl buffer AOI222 AOI2223 AOI2223H AOI222H MH1099 MH1242 PRD21 PRD29V5 Text: Features • High Speed - 170 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.6 Million Used Gates and 596 pads, with 3.3V, 3V, and 2.5V libraries • System Level Integration Technology Cores on request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:	Original	250MHz 220MHz 800MHz 5962-01B01 PO88 ttl buffer AOI222 AOI2223 AOI2223H AOI222H MH1099 MH1242 PRD21 PRD29V5	PDF
AOI222 Abstract: AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter Text: Features • High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries • System Level Integration Technology Cores on Request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:	Original	5962-01B01 4138E AOI222 AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter	PDF

SRAM SPICE Search Results

SRAM SPICE Result Highlights (5)

SRAM SPICE Datasheets Context Search

58LC32K

bsu 479

static SRAM single port

Untitled

FKC2

Untitled

diagram power supply LG 32 lh 35 fr

AN1004

80486 microprocessor block diagram and pin diagrams

10256K

Untitled

Untitled

FIFO36

FIFO36

transistor GW 93 H

max 1786

ATL35

ATL35

ATMEL 634

Untitled

MH1099

ATMEL 634

PO88

AOI222