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    SSTL_18 Search Results

    SSTL_18 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74SSTVF16857PAG Renesas Electronics Corporation 14-Bit Registered Buffer with SSTL I/O Visit Renesas Electronics Corporation
    74SSTV16857PAG Renesas Electronics Corporation 14-Bit Registered Buffer with SSTL I/O Visit Renesas Electronics Corporation
    74SSTV16857PAG8 Renesas Electronics Corporation 14-Bit Registered Buffer with SSTL I/O Visit Renesas Electronics Corporation
    74SSTVF16857PAG8 Renesas Electronics Corporation 14-Bit Registered Buffer with SSTL I/O Visit Renesas Electronics Corporation
    74SSTVN16859CPAG8 Renesas Electronics Corporation 13-Bit to 26-Bit Registered Buffer with SSTL I/O Visit Renesas Electronics Corporation

    SSTL_18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    A115-A

    Abstract: C101 SN74SSTU32864D SN74SSTU32864DGKER TOP-SIDE MARKING H2 SU864D
    Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout


    Original     		PDF SN74SSTU32864D 25-BIT SCES623A 14-Bit A115-A C101 SN74SSTU32864D SN74SSTU32864DGKER TOP-SIDE MARKING H2 SU864D

    D869

    Abstract: marking nb IDT74SSTU32D869
    Text: IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 14-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTU32D869 FEATURES: • • • • • • • • 1.8V Operation Designed to drive low impedance nets SSTL_18 style clock and data inputs


    Original     		PDF IDT74SSTU32D869 14-BIT 100mA MIL-STD-883, 200pF, 150-pin 10MHz, D869 marking nb IDT74SSTU32D869

    Untitled

    Abstract: No abstract text available
    Text: CBTW28DD14 14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications Rev. 6 — 25 July 2014 Product data sheet 1. General description This 14-bit bus switch/multiplexer MUX is designed for 1.5 V or 1.8 V supply voltage operation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS


    Original     		PDF CBTW28DD14 14-bit CBTW28DD14

    is46dr32801a-5bbla1

    Abstract: 126-ball IS46DR32801A
    Text: IS43DR32800A, IS43/46DR32801A 8Mx32 256Mb DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O SSTL_18-compatible • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS)


    Original     		PDF IS43DR32800A, IS43/46DR32801A 8Mx32 256Mb 18-compatible) DDR2-667D IS43DR32801A-3DBLI DDR2-533C IS43DR32801A-37CBLI DDR2-400B is46dr32801a-5bbla1 126-ball IS46DR32801A

    IS43DR83200A

    Abstract: IS43DR16160A-3DBLI datasheet IS43DR16160A-37CBLI IS43DR83200A-37CBLI IS43DR32160A DDR2 x32
    Text: IS43DR83200A IS43/46DR16160A, IS43DR32160A 32Mx8, 16Mx16, 16Mx32 stacked die DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle


    Original     		PDF IS43DR83200A IS43/46DR16160A, IS43DR32160A 32Mx8, 16Mx16, 16Mx32 18-compatible) IS43DR32160A-37CBLI 400Mhz IS43DR32160A-5BBLI IS43DR83200A IS43DR16160A-3DBLI datasheet IS43DR16160A-37CBLI IS43DR83200A-37CBLI IS43DR32160A DDR2 x32

    Untitled

    Abstract: No abstract text available
    Text: IS43/46DR83200A IS43/46DR16160A 32Mx8, 16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O SSTL_18-compatible • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS)


    Original     		PDF IS43/46DR83200A IS43/46DR16160A 32Mx8, 16Mx16 18-compatible) 256Mb -40oC 105oC, 105oC

    Untitled

    Abstract: No abstract text available
    Text: SN74CBTU4411 11ĆBIT 1ĆOFĆ4 FET MULTIPLEXER/DEMULTIPLEXER 1.8ĆV DDRĆII SWITCH WITH CHARGE PUMP AND PRECHARGED OUTPUTS SCDS192 − APRIL 2005 D Supports SSTL_18 Signaling Levels D Suitable for DDR-II Applications D D−Port Outputs Are Precharged by Bias


    Original     		PDF SN74CBTU4411 SCDS192 000-V A114-B,

    IDT74SSTU32864D

    Abstract: No abstract text available
    Text: IDT74SSTU32864D 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O FEATURES: IDT74SSTU32864D DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs


    Original     		PDF IDT74SSTU32864D 100mA MIL-STD-883, 200pF, 96-pin SSTU32864D 25-bit 14-bit 10MHz, IDT74SSTU32864D

    Untitled

    Abstract: No abstract text available
    Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout


    Original     		PDF SN74SSTU32864C 25-BIT SCES542B 14-Bit

    EM68A16CWQB-25H

    Abstract: EM68A16CWQB 2TWR EM68A Etron em68a16
    Text: EtronTech EM68A16CWQB 16M x 16 bit DDRII Synchronous DRAM SDRAM Etron Confidential Advanced (Rev 1.1 July / 2010) Features Overview • JEDEC Standard Compliant • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Power supplies: VDD & VDDQ = +1.8V ± 0.1V


    Original     		PDF EM68A16CWQB 18-compatible) 333/400MHz 84-Ball EM68A16CWQB-25H EM68A16CWQB 2TWR EM68A Etron em68a16

    LA2 DT2

    Abstract: BGA64 TC59LM906AMG TC59LM914AMG P-BGA64-1317-1
    Text: TC59LM914/06AMG-37,-50 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 512Mbits Network FCRAM1 SSTL_18 / HSTL_Interface − 4,194,304-WORDS x 8 BANKS × 16-BITS − 8,388,608-WORDS × 8 BANKS × 8-BITS DESCRIPTION Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM914/06AMG is Fast Cycle


    Original     		PDF TC59LM914/06AMG-37 512Mbits 304-WORDS 16-BITS 608-WORDS TC59LM914/06AMG TC59LM914AMG TC59LM906AMG LA2 DT2 BGA64 P-BGA64-1317-1

    Untitled

    Abstract: No abstract text available
    Text: IS43/46DR16160B 16Mx16 DDR2 DRAM PRELIMINARY INFORMATION NOVEMBER 2012 FEATURES DESCRIPTION •฀ VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V •฀ JEDEC standard 1.8V I/O SSTL_18-compatible •฀ Double data rate interface: two data transfers per clock cycle


    Original     		PDF IS43/46DR16160B 16Mx16 18-compatible) sS46DR16160B-37CBLA1 DDR2-533C IS46DR16160B-37CBA1 -40oC 105oC, 105oC

    C101

    Abstract: CTU4411 SN74CBTU4411 SN74CBTU4411GSTR
    Text: SN74CBTU4411 11ĆBIT 1ĆOFĆ4 FET MULTIPLEXER/DEMULTIPLEXER 1.8ĆV DDRĆII SWITCH WITH CHARGE PUMP AND PRECHARGED OUTPUTS SCDS192 − APRIL 2005 D Supports SSTL_18 Signaling Levels D Suitable for DDR-II Applications D D−Port Outputs Are Precharged by Bias


    Original     		PDF SN74CBTU4411 11BIT SCDS192 000-V A114-B, SN74plifiers C101 CTU4411 SN74CBTU4411 SN74CBTU4411GSTR

    IS43DR82560B

    Abstract: IS46DR16128B IS43DR16128B-25EBLI IS46DR16128B-3DBLA1 IS43DR16128B-25EBL
    Text: IS43/46DR82560B IS43/46DR16128B 256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O SSTL_18-compatible • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS)


    Original     		PDF IS43/46DR82560B IS43/46DR16128B 256Mx8, 128Mx16 18-compatible) -40oC DDR2-667D IS46DR16128B-3DBLA1 IS46DR16128B-3DBA1 IS43DR82560B IS46DR16128B IS43DR16128B-25EBLI IS43DR16128B-25EBL

    AS4C128M8D2

    Abstract: No abstract text available
    Text: AS4C128M8D2 128M x 8 bit DDRII Synchronous DRAM SDRAM Confidential Advanced (Rev. 1.0, Jun. /2013) Features Overview • JEDEC Standard Compliant  JEDEC standard 1.8V I/O (SSTL_18-compatible)  Power supplies: VDD & VDDQ = +1.8V  0.1V  Operating temperature range


    Original     		PDF AS4C128M8D2 18-compatible) AS4C128M8D2

    Untitled

    Abstract: No abstract text available
    Text: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input


    Original     		PDF IDT74SSTU32865 28-BIT 100mA MIL-STD-883, 200pF, 160-pin SSTU32865

    is43dr32800a

    Abstract: IS43DR32801A DDR2 SDRAM IS46DR32801A-5BBLA2
    Text: IS43DR32800A, IS43/46DR32801A 8Mx32 256Mb DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O SSTL_18-compatible • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS)


    Original     		PDF IS43DR32800A, IS43/46DR32801A 8Mx32 256Mb 18-compatible) -40oC DDR2-400B IS46DR32801A-5BBLA1 is43dr32800a IS43DR32801A DDR2 SDRAM IS46DR32801A-5BBLA2

    Untitled

    Abstract: No abstract text available
    Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout


    Original     		PDF SN74SSTU32864D 25-BIT SCES623A 14-Bit

    Untitled

    Abstract: No abstract text available
    Text: Advanced Power Electronics Corp. AP1270AMP 2.5A SINK/SOURCE BUS TERMINATION REGULATOR FEATURES DESCRIPTIOON Ideal for DDR-I, DDR-II and DDR-III VTT Applications Sink and Source up to 2.5Amp Integrated Power MOSFETs Generates Termination Voltage for SSTL_2, SSTL_18,


    Original     		PDF AP1270AMP AP1270AMP 125oC 75oC/W 1270AMP

    EM44BM1684LBA

    Abstract: bga 84 BGA84 BGA-84 DDR2-667 em44bm1684lba-3f
    Text: eorex EM44BM1684LBA 512Mb 8Mx4Bank×16 Double DATA RATE 2 SDRAM Features Description • JEDEC Standard VDD/VDDQ=1.8V ± 0.1V. • All inputs and outputs are compatible with SSTL_18 interface. • Fully differential clock inputs (CK,/CK) operation. • 4 Banks


    Original     		PDF EM44BM1684LBA 512Mb BGA-84 EM44BM1684LBA bga 84 BGA84 DDR2-667 em44bm1684lba-3f

    Untitled

    Abstract: No abstract text available
    Text: IS43/46DR86400D IS43/46DR16320D 64Mx8, 32Mx16 DDR2 DRAM APRIL 2014 FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O SSTL_18-compatible • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS)


    Original     		PDF IS43/46DR86400D IS43/46DR16320D 64Mx8, 32Mx16 18-compatible) DDR2-800D IS46DR16320D-25DBLA2 DDR2-667D IS46DR16320D-3DBLA2 IS43/46DR86400D,

    AS4C64M8D2

    Abstract: No abstract text available
    Text: AS4C64M8D2 512M – 64M x 8 bit DDRII Synchronous DRAM (SDRAM) Confidential (Rev. 1.0, Feb. /2014) Features Overview • JEDEC Standard Compliant  JEDEC standard 1.8V I/O (SSTL_18-compatible)  Power supplies: VDD & VDDQ = +1.8V  0.1V  Operating temperature: 0 – 95 °C


    Original     		PDF AS4C64M8D2 18-compatible) AS4C64M8D2

    PI74

    Abstract: PI74SSTU32866 Q13A SN74SSTU32866 SSTU32866
    Text: PI74SSTU32866 25-bit 1:1 or 14-bit 1:2 Configurable Registered Buffer with Parity Product Features Product Description • PI74 SSTU32866 is designed for low-voltage operation, VDD = 1.8V • Supports Low Power Standby Operation • All Inputs are SSTL_18 Compatible, except RST, C0, C1,


    Original     		PDF PI74SSTU32866 25-bit 14-bit SSTU32866 PS8739 PI74 PI74SSTU32866 Q13A SN74SSTU32866

    Untitled

    Abstract: No abstract text available
    Text: IS43/46DR32160C 16Mx32 512Mb DDR2 DRAM FEATURES ADVANCED INFORMATION OCTOBER 2010 DESCRIPTION • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O SSTL_18-compatible • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS)


    Original     		PDF IS43/46DR32160C 16Mx32 512Mb 18-compatible) -40oC DDR2-400B IS46DR32160C-5BBLA1