CORE i3 ARCHITECTURE
Abstract: str 6554 DMC TOOL GP32 ST100 multimedia board core i3 addressing modes str f 6554 DMC 5044 linear handbook ST100
Text: ST100 DSP-MCU CORE Architecture Overview Handbook ST100 DSP-MCU CORE Architecture Overview Handbook Version 1.1 AZERTY Architecture Overview Handbook I I.1 I.2 I.3 INTRODUCTION THE ST100 CORE ARCHITECTURE ST100 CORE APPLICATIONS ST100 CORE ROADMAP ST100 CORE FEATURES
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ST100
GP16-INSTRUCTIONS
GP32-INSTRUCTIONS
CORE i3 ARCHITECTURE
str 6554
DMC TOOL
GP32
ST100 multimedia board
core i3 addressing modes
str f 6554
DMC 5044
linear handbook
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GHS linker file format
Abstract: ST100 BIT 3713 ST110 GP32 ST120 ST140 ST180 MCU2000
Text: www.st.com/st100 Version 6.0a - January 2000 page 1 1 CU T S -M P S D TOPICS ST100 Family Overview ST120 Dual MAC Architecture ST120 Implementation ST100 development toolset CU M it -b 6 1 SP U D C it it M -b 6 b 1 32 page 2 ST100 DSP-MCU CORE ST100 Key Advantages.
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com/st100
ST100
ST120
GHS linker file format
BIT 3713
ST110
GP32
ST140
ST180
MCU2000
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BIT 3713
Abstract: GP32 ST100 ST100-4W ST1000 MOPS
Text: ST100: A new DSP-MCU Core Architecture for Embedded Applications Architecture Goals STMicroelectronics’ innovative ST100 DSP-MCU processor core architecture has been conceived specifically for embedded applications in custom system-on-chip products for demanding markets like cellular phones, hard disk drives, engine
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ST100:
ST100
16-bit
32-bit
128-bit
BIT 3713
GP32
ST100-4W
ST1000
MOPS
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ST122
Abstract: GP32 1x40 PIN DMC TOOLS AM32 ST100 ST140 soc x1000
Text: ST122 DSP CORE OVERVIEW HANDBOOK Release 1.0 June 2003 1/54 2/54 TABLE OF CONTENTS ST122 DSP OVERVIEW HANDBOOK TABLE OF CONTENTS PAGE 1 INTRODUCING THE ST100 DSP FAMILY . 6 1.1 MAIN TARGET APPLICATIONS OF ST100 DSP CORES .
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ST122
ST100
ST122OH
GP32
1x40 PIN
DMC TOOLS
AM32
ST140
soc x1000
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GHS linker
Abstract: ST100 GHS linker file format GHS multi green hills license ST-100 MULTI IDE LINKER C
Text: ST100 DSP-MCU Core Toolset The ST100 DSP-MCU Core from STMicroelectronics is an innovative new processor core for embedded applications. Based on a 32-bit Load/Store architecture supporting both MCU and DSP code, it replaces a combination of DSP and micro cores in
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ST100
32-bit
ST100
GHS linker
GHS linker file format
GHS multi
green hills license
ST-100
MULTI IDE LINKER C
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STMicroelectronics date code format
Abstract: GP32 ST100 dsp ST100 ST120
Text: ST100 ST100 DSP CORES DATA BRIEF 1 • ■ ■ ■ ■ ■ ■ ■ ■ FEATURES State-of-the-art DSP core architecture – Complete & optimized memory systems – Multicore solutions – Standard or specific tightly coupled peripherals libraries Advanced Load/store Architecture
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ST100
ST100
16-bit
32-bit
STMicroelectronics date code format
GP32
ST100 dsp
ST120
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PIC dmx example codes
Abstract: fir filter with lms algorithm in vhdl code ST100 dsp vhdl code for FFT 32 point DMX chip 32 bit ALU vhdl code ST140 GP32 32 bit ALU vhdl DMC TOOLS
Text: ST140 DSP CORE OVERVIEW HANDBOOK Release 1.0 TABLE OF CONTENTS ST140 DSP OVERVIEW HANDBOOK TABLE OF CONTENTS PAGE PREFACE . 7 1 INTRODUCING THE ST100 DSP CORES FAMILY .
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ST140
ST100
ST140OH
PIC dmx example codes
fir filter with lms algorithm in vhdl code
ST100 dsp
vhdl code for FFT 32 point
DMX chip
32 bit ALU vhdl code
GP32
32 bit ALU vhdl
DMC TOOLS
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GP32
Abstract: ST100 integer operation DSP
Text: STMicroelectronics Innovative new Processor Core for Embedded Applications Combines DSP and Microprocessor Features. Aimed primarily at system-on-chip applications, ST100 DSP-MCU core provides high performance, low power consumption, ease of development and flexibility.
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ST100
16/May/2000
GP32
integer operation DSP
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GP32
Abstract: ST100 ST120 ST120-DSP memory bandwidth ST100 multimedia board
Text: ST Solutions for Embedded Applications ST100 DSP-MCU Cores High Performance DSP-MCU Core 32 bit load/store architecture with multiple calculation units Scaleable architecture easily extensible to 64 bits Three selectable instruction sets: GP16, GP32 and SLIW
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ST100
40-bit
ST100
GP32
ST120
ST120-DSP
memory bandwidth
ST100 multimedia board
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LB598
Abstract: LB156 B0017 ST122 LB807 LB102 B0006 ST100 LB742 LB142
Text: AN1999 APPLICATION NOTE Tuning C code with the STCC compiler INTRODUCTION The ST100® processor family has been designed to provide a DSP solution that implements the best tradeoff between the following factors: Compiler friendliness. Reduced code size.
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AN1999
ST100®
ST100
LB598
LB156
B0017
ST122
LB807
LB102
B0006
LB742
LB142
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decoder huffman
Abstract: huffman encoding Huffman AN1443 ST100 ST120 MEMORY128 ST120DSP
Text: AN1443 APPLICATION NOTE ST100 VIDEO LIBRARY Baseline JPEG Encoding and Decoding on the ST120DSP By Maurizio Colombo ABSTRACT This application note shows the results of porting the JPEG application for a SW implementation on ST120DSP. JPEG standard is very generic and includes different techniques. The Baseline method is by
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AN1443
ST100
ST120DSP
ST120DSP.
decoder huffman
huffman encoding
Huffman
AN1443
ST120
MEMORY128
ST120DSP
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evrc
Abstract: ST122 IS-95 MS support evrc AN1997 vocoder implementation ST100 dsp Viterbi Decoder GP32 ST100 ST140
Text: AN1997 APPLICATION NOTE IS-127 Enhanced Variable Rate Speech Coder EVRC Multi-channel Implementation on the ST122 DSP-MCU ABSTRACT The purpose of this application note is to provide a detailed description of the Enhanced Variable Rate Coding (EVRC) vocoder, Speech Service Option 3. This application note also provides a detailed description of the EVRC vocoder multi-channel implemented solution and its performances on to the STMicroelectronics ST122 DSP-MCU system, which is based on the ST100 architecture.
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AN1997
IS-127
ST122
ST100®
32-bit
ST122
ST100
evrc
IS-95 MS support evrc
AN1997
vocoder implementation
ST100 dsp
Viterbi Decoder
GP32
ST140
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GP32
Abstract: ST100 ST120 bluetooth interfacing design code
Text: Disk Drive Solutions High Performance DSP-MCU Core 32 bit load/store architecture with multiple calculation units Scaleable architecture easily extensible to 64 bits Three selectable instruction sets: GP16, GP32 and SLIW Supports arithmetic on 32 bit, saturating, 40 bit extended precision,
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ST100
GP32
ST120
bluetooth interfacing design code
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GP32
Abstract: ST100 multimedia board ST100 ST120 "vector instructions" saturation
Text: Disk Drive Solutions High Performance DSP-MCU Core 32-bit load/store architecture with multiple calculation units Scaleable architecture easily extensible to 64 bits Three selectable instruction sets: GP16, GP32 and SLIW Supports arithmetic on 32-bit, saturating, 40-bit extended precision,
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32-bit
32-bit,
40-bit
ST100
com/st100
GP32
ST100 multimedia board
ST120
"vector instructions" saturation
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AN1881
Abstract: G711 ST122 G.711 CHIP SET ST100 multimedia evaluation board GP32 ST100 multimedia board ST100 ST140 ST100 dsp
Text: AN1881 APPLICATION NOTE G711 Speech Codec: Multichannel Implementation on the ST122 DSP-MCU ABSTRACT The purpose of this application note is to provide a detailed description of the Multichannel G711 speech codec optimized for performances on the STMicroelectronics STTM ST122 DSP-MCU system, which is
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AN1881
ST122
ST100®
32-bit
ST100
AN1881
G711
G.711 CHIP SET
ST100 multimedia evaluation board
GP32
ST100 multimedia board
ST140
ST100 dsp
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RPE-LTP
Abstract: AN1860 GSM circuit diagram project ST122 ST100 dsp GP32 RPE 113 gsm module with microcontroller ST140 ST100
Text: AN1860 APPLICATION NOTE GSM 06.10 Full Rate Coder Multi-channel Implementation on the ST122 DSP-MCU ABSTRACT The purpose of this application note is to provide a detailed description of the GSM 06.10 Full Rate vocoder. This application note also attempts to provide a description of the GSM 06.10 Full Rate vocoder
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AN1860
ST122
ST100®
32-bit
ST100
RPE-LTP
AN1860
GSM circuit diagram project
ST100 dsp
GP32
RPE 113
gsm module with microcontroller
ST140
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lattice codec
Abstract: ST122 gsm circuit diagram project AN1998 GP32 ST100 ST140 VOCODERS voip ST100-DSP
Text: AN1998 APPLICATION NOTE Half Rate Speech Coder HR Multi-channel Implementation on the ST122 DSP-MCU ABSTRACT The purpose of this application note is to provide a detailed description of porting and an optimized implementation of a low bit rate speech coder based on the ETSI GSM-Half Rate (HR) vocoder implementation
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AN1998
ST122
ST100®
32-bit
128-bit
ST100
lattice codec
gsm circuit diagram project
AN1998
GP32
ST140
VOCODERS voip
ST100-DSP
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30424
Abstract: 31.356 fract16 lgp32 25832 GHS 59 27132 FFT128 30349 AN1444
Text: AN1444 APPLICATION NOTE General Purpose DSP Library for the ST120 DSP By David DAUBOIS 1 - INTRODUCTION This document presents a set of optimized DSP functions for C programmers on the ST120 DSP. These functions are typically used in real time applications where execution time is critical.
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AN1444
ST120
AN1444
30424
31.356
fract16
lgp32
25832
GHS 59
27132
FFT128
30349
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12V relay 4098
Abstract: AD5379 AD5380BST-3 AD5380BST-5 AD5381BST-3 AD5381BST-5
Text: 40-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage-Output DAC AD5379 Interface options: Parallel interface DSP/microcontroller-compatible, 3-wire serial interface 2.5 V to 5.5 V JEDEC-compliant digital levels SDO daisy-chaining option Power-on reset
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40-Channel,
14-Bit,
AD5379
40-channel
108-lead
MO-192-AAD-1
BC-108-2)
AD5379ABC
EVAL-AD5379EB
12V relay 4098
AD5379
AD5380BST-3
AD5380BST-5
AD5381BST-3
AD5381BST-5
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Untitled
Abstract: No abstract text available
Text: 32-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage Output DAC AD5378 FEATURES Interface options Parallel interface DSP/microcontroller-compatible 3-wire serial interface 2.5 V to 5.5 V JEDEC-compliant digital levels SDO daisy-chaining option Power-on reset
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32-Channel,
14-Bit,
AD5378
32-channel
108-lead
MO-192-AAD-1
108-Ball
BC-108-2)
AD5378ABC
AD5378ABCZ1
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ADSP-2185N
Abstract: ADSP-2100 ADSP-2184N ADSP-2186N ADSP-2187N ADSP-2189M D1881 ca144
Text: a DSP Microcomputer ADSP-218xN Series PERFORMANCE FEATURES 12.5 ns Instruction Cycle Time @1.8 V Internal , 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle
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ADSP-218xN
ADSP-2100
100-Lead
ADSP-2185N
ADSP-2184N
ADSP-2186N
ADSP-2187N
ADSP-2189M
D1881
ca144
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ADSP-2185N
Abstract: MN1280-R ADSP-2100 ADSP-2184N ADSP-2186N ADSP-2187N ADSP-2189M
Text: a DSP Microcomputer ADSP-218xN Series PERFORMANCE FEATURES 12.5 ns Instruction Cycle Time @1.8 V Internal , 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle
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ADSP-218xN
ADSP-2100
100-Lead
ADSP-2185N
MN1280-R
ADSP-2184N
ADSP-2186N
ADSP-2187N
ADSP-2189M
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relay 4098
Abstract: 12V relay 4098 T154 AD5378 AD5379ABC AD5380BST-3 AD5380BST-5 AD5381BST-3 AD5381BST-5 BC-108
Text: 32-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage Output DAC AD5378 Preliminary Technical Data Interface options Parallel interface DSP/microcontroller-compatible 3-wire serial interface 2.5 V to 5.5 V JEDEC-compliant digital levels SDO daisy-chaining option
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32-Channel,
14-Bit,
AD5378
32-channel
108-lead
MO-192-AAD-1
BC-108-2)
AD5378ABC
AD5378ABCZ1
relay 4098
12V relay 4098
T154
AD5378
AD5379ABC
AD5380BST-3
AD5380BST-5
AD5381BST-3
AD5381BST-5
BC-108
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ADSP-2185N
Abstract: ADSP-2100 ADSP-2184N ADSP-2186N ADSP-2187N ADSP-2189M ADSP-2188
Text: a DSP Microcomputer ADSP-218xN Series PERFORMANCE FEATURES 12.5 ns Instruction Cycle Time @1.8 V Internal , 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle
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ADSP-218xN
ADSP-2100
100-Lead
ADSP-2185N
ADSP-2184N
ADSP-2186N
ADSP-2187N
ADSP-2189M
ADSP-2188
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