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    Hosa Technology STP-201RR

    Connector Type A:1/4" Stereo Phone Plug; Connector Type B:1/4" Mono Phone Plug X 2; Cable Length - Imperial:3.28Ft; Cable Length - Metric:1M; Jacket Color:Black; Product Range:- Rohs Compliant: Yes |Hosa STP-201RR
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    Newark STP-201RR Bulk 7 1
    • 1 $7.34
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    Hosa Technology STP-201

    Connector Type A:1/4" Stereo Phone Plug; Connector Type B:1/4" Mono Phone Plug X 2; Cable Length - Imperial:3.28Ft; Cable Length - Metric:1M; Jacket Color:Black; Product Range:- Rohs Compliant: Yes |Hosa STP-201
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    Newark STP-201 Bulk 1
    • 1 $13.95
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    Sun Microsystems, Inc. STP2016QFP

    50 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100
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    Quest Components STP2016QFP 24
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    STP201 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    STP2016

    Abstract: SuperSPARC mbus 10 application STP2011 STP2016QFP mbus MCLK11 MOSC STP2012
    Text: STP2016 July 1997 Clock-2 Generator System Clock Generator DATA SHEET DESCRIPTION The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at


    Original     		PDF STP2016 STP2016 64-bit PQFP100 100-Pin STP2016QFP SuperSPARC mbus 10 application STP2011 STP2016QFP mbus MCLK11 MOSC STP2012

    53C90A

    Abstract: ncr53c90 STP2012 53C90 AD12 AM7990 STP2013 EIRQ15 STP2011 53c90 scsi
    Text: STP2012QFP July 1997 DMA2 DATA SHEET SBus DMA Controller DESCRIPTION The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DMA access to one AMD Am7990 Local Area Network Controller for the Ethernet (LANCE), one NCR 53C90 SCSI controller (ESP), and one programmable Centronics-type parallel port. The


    Original     		PDF STP2012QFP STP2012 Am7990 53C90 STP2012PQFP 160-Pin STP2012 53C90A ncr53c90 AD12 STP2013 EIRQ15 STP2011 53c90 scsi

    STP2014

    Abstract: MK48T08-1 EBA11 STP2104 AmZ8 AD27 AD29 AD30
    Text: STP2014.frm 1 Mon Jul 7 08:25:34 1997 STP2014 July 1997 SEC DATA SHEET SBus-to-EBus Controller DESCRIPTION The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the interrupt control and steering logic, the timer/counter registers, reset logic, and miscellaneous registers. The


    Original     		PDF STP2014 STP2014 STP2104 STP2014PQFP 160-Pin MK48T08-1 EBA11 AmZ8 AD27 AD29 AD30

    STP2013

    Abstract: Mbus master 250 slave circuit STP2013PGA-50 m-bus mbus STP2011 STP2013PGA50 MAD44
    Text: STP2013PGA-50 July 1997 EMC DATA SHEET Error-Correcting Memory Controller DESCRIPTION The STP2013 Error-Correcting Memory Controller control mechanism consists of a central arbiter that selects between MBus and graphics-request masters, while monitoring periodic refresh and VIO preemptive interrupts. Satellite state machines are granted execution by the arbiter in response to a buffered request. Stalled


    Original     		PDF STP2013PGA-50 STP2013 STP2013PGA 299-Pin STP2013 Mbus master 250 slave circuit STP2013PGA-50 m-bus mbus STP2011 STP2013PGA50 MAD44

    mbus master circuit

    Abstract: STP2011 MAD44 mbus 10 application three phase ESC circuit diagrams MAD50
    Text: STP2011PGA-50 July 1997 MSI DATA SHEET MBus-to-SBus Interface DESCRIPTION The STP2011 MBus-to-SBus Interface MSI provides an interface between the MBus and the SBus and controls access to the I/O subsystem. The MSI consists of two main functional blocks: the Memory Subsystem and the I/O Subsystem.


    Original     		PDF STP2011PGA-50 STP2011 STP2011PGA 279-Pin STP2011 mbus master circuit MAD44 mbus 10 application three phase ESC circuit diagrams MAD50

    STP2018TAB

    Abstract: STP2018 m-bus
    Text: STP2018 July 1997 MSBI MBus to SBus Interface DATA SHEET DESCRIPTION The STP2018 MBus to SBus Interface MSBI provides a bus bridge between two different busses used by a number of SPARC microprocessors and controls access to the I/O subsystem. The MBus is designed for multiprocessing (MP),


    Original     		PDF STP2018 STP2018 64-bit 288-Lead STP2018TAB STP2018TAB m-bus

    STP2012

    Abstract: SuperSPARC STP2016QFP
    Text: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at


    OCR Scan     		PDF STP2016 STP2016 64-bit 100-Pin STP2016Q STP2012 SuperSPARC STP2016QFP

    Untitled

    Abstract: No abstract text available
    Text: STP2012QFP S un M ic r o e l e c t r o n ic s J u ly 1997 DMA2 DATA SHEET SBus DMA Controller D e s c r ip t io n The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DM A access to one AM D Am 7990 Local Area N etw ork Control­


    OCR Scan     		PDF STP2012QFP STP2012 53C90 STP2012PQ 160-Pin STP2012

    mbus 10 application

    Abstract: STP2012 TP2018
    Text: S un M icroelectronics July 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing


    OCR Scan     		PDF STP2016 64-bit MCLK10 88S88g88 8S3885B 100-Pin mbus 10 application STP2012 TP2018

    Untitled

    Abstract: No abstract text available
    Text: S un M icro electro nics July 1997 MSBI DATA SHEET MBus to SBus Interface D e s c r ip t io n The STP2018 MBus to SBus Interface MSBI provides a bus bridge between two different busses used by a number of SPARC microprocessors and controls access to the I/O subsystem. The MBus is designed for


    OCR Scan     		PDF STP2018 64-bit 286-Lead 055-P 25x71 STP2018

    STP2012QFP

    Abstract: No abstract text available
    Text: STP 2Û 12Q FP S un M ic r o e le c tr o n ic s July 1997 DMA2 DATA SHEET SBus DMA Controller D e s c r ip t io n The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DMA access to one AM D Am 7990 Local Area N etw ork Control­


    OCR Scan     		PDF STP2012 53C90 160-Pin STP201 STP2012QFP

    STP201

    Abstract: No abstract text available
    Text: SPA RC T echrdogy Business N ovem ber 1994 S T P 2016 DATA SHEET D C lo c k s G e n e ra to r escription The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multi­


    OCR Scan     		PDF STP2016 64-bit STB3DS13-1-894 STP201

    sba20

    Abstract: mbus master circuit
    Text: S un M icro electro nics July 1997 MSI DATA SHEET MBus-to-SBus Interface D e s c r ip t io n The STP2011 MBus-to-SBus Interface MSI provides an interface between the MBus and the SBus and con­ trols access to the 1 /O subsystem. The MSI consists of two main functional blocks: the Memory Subsystem


    OCR Scan     		PDF STP2011 sba20 mbus master circuit

    IS279

    Abstract: mbus master circuit
    Text: S T P 2 0 1 1 P G A -5 0 S un M ic r o e le c t r o n ic s July 1997 MSI DATA SHEET MBus-to-SBus Interface D e s c r ip t io n The STP2011 MBus-to-SBus Interface MSI provides an interface between the MBus and the SBus and controls access to the I/O subsystem. The MSI consists of two main functional blocks: the Memory Subsystem and the I/O Subsystem.


    OCR Scan     		PDF STP2011 STP2011PGA 279-Pin STP2011 IS279 mbus master circuit

    Untitled

    Abstract: No abstract text available
    Text: S T P 2 0 1 1 P G A -5 0 S un M ic r o e l e c t r o n ic s J u ly 1 9 9 7 MSI DATA SHEET MBus-to-SBus Interface D e s c r ip t io n The STP2011 M Bus-to-SBus Interface MSI provides an interface betw een the M Bus and the SBus and con­ trols access to the I / O subsystem. The M SI consists of two m ain functional blocks: the M em ory Subsystem


    OCR Scan     		PDF STP2011 STP2011PGA-50 11PGA STP2011

    Untitled

    Abstract: No abstract text available
    Text: STP2014 S un M ic r o e l e c t r o n ic s July 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the inter­


    OCR Scan     		PDF STP2014 STP2014 STP2104 STP2014PQFP 160-Pin

    M-BUS

    Abstract: No abstract text available
    Text: S un M ic r o e l e c t r o n ic s July 1997 MSBI MBus to SBus Interface DATA SHEET D e s c r ip t io n The STP2018 MBus to SBus Interface MSBI provides a bus bridge between two different busses used by a number of SPARC microprocessors and controls access to the I/O subsystem. The MBus is designed for multiprocessing (MP),


    OCR Scan     		PDF STP2018 64-bit STP2018 288-Lead STP2018TAB M-BUS

    Untitled

    Abstract: No abstract text available
    Text: S T P 2 Û1 3 P G A -50 S un M ic r o e le c t r o n ic s July 1997 EMC DATA SHEET Error-Correcting M emory Controller D e s c r ip t io n The STP2013 Error-C orrecting M em ory C ontroller control m echanism consists of a central arbiter that selects betw een M Bus and graphics-request m asters, w hile m onitoring periodic refresh and VIO preem ptive inter­


    OCR Scan     		PDF STP2013 STP201 299-Pin STP2013

    D37M

    Abstract: No abstract text available
    Text: STP2013PGA-50 S un M ic r o e l e c t r o n ic s J u ly 1997 EMC DATA SHEET Error-Correcting Memory Controller D e s c r ip t io n The STP2013 Error-Correcting M em ory Controller control m echanism consists of a central arbiter that selects betw een M Bus and graphics-request masters, while m onitoring periodic refresh and VIO preem ptive inter­


    OCR Scan     		PDF STP2013PGA-50 STP2013 DR0000000000000000000 SSSSSSS00000000000® TP2013PG 299-Pin D37M

    Untitled

    Abstract: No abstract text available
    Text: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1 9 9 7 Clock-2 Generator System Clock Generator DATA SHEET D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for com ponents on the SBus and MBus. The M Bus and SBus are used by SPARC processors, such as SuperSPARC™. The M Bus is designed for multiprocessing


    OCR Scan     		PDF STP2016 STP2016 64-bit 100-Pin TP2016Q

    STP2014QFP

    Abstract: No abstract text available
    Text: STP2014.frm 1 Mon Jul 7 08:25:34 1997 S un M e ic r o e l e c t r o n ic s J u ly 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/m ouse. The STP2014 also houses the inter­


    OCR Scan     		PDF STP2014 STP2104 STP2014 TP2014PQ 160-Pin STP2014QFP

    SB013

    Abstract: STP2012 53c90 NCR
    Text: S un M icro electro nics July 1997 DMA2 DATA SHEET SBus DMA Controller D e s c r ip t io n The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DMA access to one AMD Am7990 Local Area Network Control­


    OCR Scan     		PDF STP2012 Am7990 53C90 STP2012 SB013 53c90 NCR

    E-BA8

    Abstract: ISOS refer STP2104
    Text: S un M ic ro electro nics July 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the inter­


    OCR Scan     		PDF STP2014 S1T2014 STP2104 STP2014 E-BA8 ISOS refer

    Untitled

    Abstract: No abstract text available
    Text: STP2018 S un M ic r o e l e c t r o n ic s J u ly 1997 MSBI MBus to SBus Interface DATA SHEET D e s c r ip t io n The STP2018 M Bus to SBus Interface MSBI provides a bus bridge betw een two different busses used by a num ber of SPARC m icroprocessors and controls access to the I /O subsystem. The M Bus is designed for


    OCR Scan     		PDF STP2018 STP2018 64-bit 288-Lead STP2018TAB