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Microchip Technology Inc SY100S336AFC IC COUNTER/SHIFT REG 24-CERPAC+G
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SY100S336AFC Datasheets (6)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
SY100S336AFC		Micrel Semiconductor	Logic - Specialty Logic, Integrated Circuits (ICs), IC COUNTER/SHIFT REG 24-CERPAC+G		Original	PDF
SY100S336AFC		Micrel Semiconductor	ENHANCED 4-STAGE COUNTER/SHIFT REGISTER		Original	PDF
SY100S336AFC		Micrel Semiconductor	ENHANCED 4-STAGE COUNTER/SHIFT REGISTER		Original	PDF
SY100S336AFC		Synergy Semiconductor	4-STAGE COUNTER / SHIFT REGISTER		Scan	PDF
SY100S336AFC		Synergy Semiconductor	ENHANCED 4-STAGE COUNTER/SHIFT REGISTER		Scan	PDF
SY100S336AFCTR		Micrel Semiconductor	ENHANCED 4-STAGE COUNTER/SHIFT REGISTER		Original	PDF

SY100S336AFC Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
SY100S336 Abstract: SY100S336A SY100S336AFC SY100S336AJC SY100S336AJCTR F100K Text: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER FEATURES DESCRIPTION • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 1100ps ■ Sn to TC speed improved by 50% ■ Sn set-up and hold time reduced by more than 50% ■ IEE min. of –170mA ■ Industry standard 100K ECL levels	Original	PDF	700MHz 1100ps 170mA F100K 24-pin 28-pin SY100S336A SY100S336, SY100S336AJC J28-1 SY100S336 SY100S336AFC SY100S336AJC SY100S336AJCTR F100K
F100K Abstract: SY100S336 SY100S336A SY100S336AFC SY100S336AJC Text: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER Micrel, Inc. SY100S336A SY100S336A DESCRIPTION FEATURES • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 1100ps ■ Sn to TC speed improved by 50% ■ Sn set-up and hold time reduced by more than 50% ■ IEE min. of –170mA	Original	PDF	SY100S336A 700MHz 1100ps 170mA F100K 24-pin 28-pin SY100S336A SY100S336, F100K SY100S336 SY100S336AFC SY100S336AJC
F100K Abstract: SY100S336 SY100S336A SY100S336AFC SY100S336AJC SY100S336AJCTR Text: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER FEATURES DESCRIPTION • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 1100ps ■ Sn to TC speed improved by 50% ■ Sn set-up and hold time reduced by more than 50% ■ IEE min. of –170mA ■ Industry standard 100K ECL levels	Original	PDF	700MHz 1100ps 170mA F100K 24-pin 28-pin SY100S336A SY100S336, SY100S336AJC J28-1 F100K SY100S336 SY100S336AFC SY100S336AJC SY100S336AJCTR
Untitled Abstract: No abstract text available Text: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER SYNERG Y SY100S336A SEMICONDUCTOR FEATURES DESCRIPTION Max. shift frequency of 700MHz Clock to Q delay max. of 1100ps Sn to TC speed improved by 50% Sn set-up and hold time reduced by more than 50% Iee min. of -170m A	OCR Scan	PDF	SY100S336A 700MHz 1100ps -170m F100K 24-pin 28-pin
Untitled Abstract: No abstract text available Text: « ENHANCED 4-STAGE COUNTER/SHIFT REGISTER SYNERGY SY100S336A SEMICONDUCTOR FEATURES DESCRIPTION • Max. shift frequency of 700MHz T h e S Y 1 0 0 S 3 3 6 A is fu n c tio n a lly th e s a m e as th e S Y 1 0 0 S 3 3 6 , b ut has Sn to TC s p e e d and Sn s e t-u p and	OCR Scan	PDF	SY100S336A 700MHz
Untitled Abstract: No abstract text available Text: O • ira ENHANCED 4-STAGE COUNTER/SHIFT REGISTER ^ SYNERGY cvm n^A oYi 00S336A SEMICONDUCTOR FEATURES DESCRIPTION ■ Max. shift frequency of 700MHz ■ Clock to Q delay max. of 110Ops ■ Sn to TC speed improved by 50% ■ Sn set-up and hold tim e reduced by more than 50%	OCR Scan	PDF	00S336A 700MHz 110Ops F100K SY100S336A SY100S336ADC D24-1 SY100S336AFC F24-1 SY100S336AJC
F100K Abstract: SY100S336 SY100S336A SY100S336ADC Text: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER m v SYNERGY . Vim <N «4 S i i 00S336A S E M IC O N D U C T O R DESCRIPTION FEATURES • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 110Ops ■ Sn to TC speed improved by 50% ■ Sn set-up and hold time reduced by more than 50%	OCR Scan	PDF	SY100S336A 700MHz 110Ops -170mA F100K SY100S336A TD013Ã SY100S336ADC D24-1 F100K SY100S336
Untitled Abstract: No abstract text available Text: * 4-STAGE COUNTER/ SHIFT REGISTER SYNERGY SY100S336A SEMICONDUCTOR FEATU R ES DESCRIPTION • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 1lOOps ■ Sn to TC speed improved by 50% ■ Sn set-up and hold time reduced by more than 50% ■ I e e min. of -170mA	OCR Scan	PDF	SY100S336A 700MHz -170mA F100K TD013Ã SY100S336ADC D24-1 SY100S336AFC F24-1
F100K Abstract: SY100S336 SY100S336A SY100S336ADC PN800 Text: 4-STAGE COUNTER/ SHIFT REGISTER SYNERGY S EM IC O N D U C TO R FEATURES I l I l l I SY100S336A D E S C R IP T IO N Max. shift frequency of 700MHz Clock to Q delay max. of HOOps Sn to TC speed Improved by 50% Sn set-up and hold time reduced by more than 50%	OCR Scan	PDF	SY100S336A 700MHz of-170mA F100K T0013Ã SY100S336ADC D24-1 SY100S336AFC F24-1 F100K SY100S336 SY100S336A PN800