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    IR2E16

    Abstract: LS125 16CIF truth table NOT gate 74 ls126 HC 125A
    Text: LS125/125A - QUAD 3-STATE BUFFER LOW ENABLE LS126/126A - QUAD 3-STATE BUFFER (HIGH ENABLE) DESCRIPTION The T54LS/T74LS125/125A/126/126A are high speed QUAD 3-STATE BUFFERS WITH ACTIVE HIGH ENABLES fabricated in LOW POWER SCHOTTKY tecnology. B1 Plastic Package


    OCR Scan     		PDF LS125/125A LS126/126A T54LS/T74LS125/125A/126/126A T54LSXXXX T74LSXXXX LS126/126A IR2E16 LS125 16CIF truth table NOT gate 74 ls126 HC 125A

    pc014

    Abstract: LS258
    Text: a s QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS DESCRIPTION The LSTTL/MSI T54LS258/258A, T74LS258/258A s a Quad 2-Input Multiplexer with 3-state outputs. Four bits of data from two sources can be selec­ ted using a Common Data Select input. The four outputs present the selected data in the comple­


    OCR Scan     		PDF T54LS258/258A, T74LS258/258A T54LSXXXe pc014 LS258

    TDA0161 equivalent

    Abstract: 1N3393 BDX54F equivalent byt301000 bux transient voltage suppressor ST90R9 ua776mh sgs 2n3055 Transistor morocco mje13007 inmos transputer reference manual
    Text: SHORTFORM 1995 NOVEMBER 1994 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein:


    OCR Scan     		PDF

    T74LS

    Abstract: LS645 LS640 LS641
    Text: s G S-THOMSOn D7E D I Lüw P U W tK S U H U INTEGRATED CIRCUITS . _ 67C . 7^5^53? 001L3T? I ;T54LS640/641/645j I IKY D 16526 fl 7c- 5 ' 2 " 3 i PRELIMINARY DATA O CTAL BUS TRANSCEIVERS DESCRIPTION The T54LS/T74LS640/641/645 are octal bus tran­


    OCR Scan     		PDF 7t5ts37 t-52-zi IT74LS640/64Ã T54LS/T74LS640/641/645 LS640 LS641 LS645 T74LS

    LS147

    Abstract: T74LSXXX PIN 74LS147
    Text: SGS M i PRELIMINARY DATA IO-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS 16 DESCRIPTION 16 T \ [ 1 i 1 These priority Encoders decode the inputs to en­ sure that only the highest order data line is enco­ ded. All inputs and outputs data of both devices


    OCR Scan     		PDF LS147 LS148 T54/74LS148) T74LSXXX PIN 74LS147

    T74LS155

    Abstract: No abstract text available
    Text: S G S-THONS ON D7E D I 7 ^ 2 3 7 DDlblOQ 3 I LOW POWER SCHOTTKY INTEGRATED CIRCUITS 6 T C - 1 6 2 2 9 . T -6 6 -2 1 -5 5 DUAL 1-OF-4 DECODER/DEMULTIPLEXER DESC RIPTIO N The TTL/MSI T54LS155/T74LS155 and T54LS156/ T74LS156 are high speed Dual 1-of-4 Decoder/De­


    OCR Scan     		PDF T54LS155/T74LS155 T54LS156/ T74LS156 T74LS155

    LS147

    Abstract: El 3021
    Text: s G S-THOMSON 07E D | 7e]a 1-237 DDlbD?^ S | LOW POWER SCHOTTKY INTEGRATED CIRCUITS i^ l4 L S 1 4 7 /t4 8 T74LS147/148 T-66-21-57 67C 16 208 PRELIMINARY DATA 10-LINË-TO-4-L1NE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS DESCRIPTIO N These priority Encoders decode the inputs to en­


    OCR Scan     		PDF T74LS147/148 T-66-21-57 10-LIN LS147 LS148 El 3021

    TOP 244 gn

    Abstract: T74LS240 S16C
    Text: S G S-THOfISON D7E D | 7 ^ 2 3 ? DDlbÈGS b | ."'.1 LOW POWER SCHOTTKY INTEGRATED & riY T 5 4 L $ 2 4 0 /2 4 1 /2 4 4 ; p n V;T74LS240/241/244| U l K O t. U I I O _ 67C 1 6 3 3 4 , . D I . , . T - 52.-&7_ OCTAL BUFFER/LINE DRIVERS W ITH 3-STA TE OUTPUTS


    OCR Scan     		PDF T74LS240/241/244| 54LS/T74LS240/241/244 TOP 244 gn T74LS240 S16C

    Q01t

    Abstract: No abstract text available
    Text: S G S-THOnSON D7E D | 7 ^ 2 3 7 if* 00lb3bû 1 | 1 LOW POWER SCHOTTKY I a INTEGRATED CIRCUITS 67C 15497 D T-66-21-51 QUAD 2-PORT REGISTER DESCRIPTION The T54LS/T74LS398/399 are Quad 2-Port Regi­ sters. They are the logical equivalent of a quad 2-input multiplexer followed by a 4-bit edgetriggered register. Selection between two 4-bit in­


    OCR Scan     		PDF 00lb3bû T-66-21-51 T54LS/T74LS398/399 T54LS/T74LS398 T54LS/T74LS399 T54LSXXX T74LSXXX Q01t

    LS155

    Abstract: demultiplexer truth table LS156 T74LS156 74 ls 155 demultiplexer
    Text: in i ss DUAL 1-0F-4 DECODER/DEMULTIPLEXER DESCRIPTION The TTL/MSI T54LS155/T74LS155 and T54LS156/ T74LS156 are high speed Dual 1-of-4 Decoder/De­ multiplexers. These devices have two decoders with common 2-bit Address inputs and separate ga­ ted Enable inputs. Decoder “ a” has an Enable gate


    OCR Scan     		PDF T54LS155/T74LS155 T54LS156/ T74LS156 LS156 LS155 demultiplexer truth table 74 ls 155 demultiplexer

    47ls148

    Abstract: LS147 LS148 74LS147
    Text: » PRELIMINARY DATA 10-LINE-T0-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS 16 T Y V 1 16 n /y \ I DESCRIPTION 1 These priority Encoders decode the inputs to en­ sure that only the highest order data line is enco­ ded. All inputs and outputs data of both devices


    OCR Scan     		PDF 10-LINE-TO-4-LINE LS147 LS148 T54/74LS148) 47ls148 74LS147

    ls293

    Abstract: ls290 binary to BCD 8421 LS293-4-BIT LS90 LS93 3 bit ripple counter T74LS293
    Text: ses LS290-DECADE COUNTER LS293-4-BIT BINARY COUNTER DESCRIPTION T 5 4 L S /T 7 4 L S 2 9 0 and T 5 4 L S /T 7 4 L S 2 9 3 are - gn-speed 4-bit ripple type counters partitioned in•: rwo sections. E ach counter has a divide-by-two section and either a divide-by-five L S 2 90 or


    OCR Scan     		PDF LS290-DECADE LS293-4-BIT T54LS/T74LS290 T54LS/T74LS293 LS290) LS293) Vodulo-16 T54LSXXX T74LSXXX ls293 ls290 binary to BCD 8421 LS90 LS93 3 bit ripple counter T74LS293

    connecting diagram for ic 74 08

    Abstract: H2635
    Text: DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS109-109A consist of two high sjjeed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operatioji as a D flip-flop by simply


    OCR Scan     		PDF T54LS/T74LS109-109A T54LSXXX T74LSXXX connecting diagram for ic 74 08 H2635

    Untitled

    Abstract: No abstract text available
    Text: DUAL DECADE COUNTER DUAL 4-STAGE BINARY COUNTER DESCRIPTION The T54LS/T74LS390 and T54LS/T74LS393 each contain a pair of high-speed 4-stage ripple coun­ ters. Each half of the LS390 is partitioned Into a divide-by-two section and a divide-by-five section,


    OCR Scan     		PDF T54LS/T74LS390 T54LS/T74LS393 LS390 LS393 Modulo-16 LS393, LS390 LS390/393

    Untitled

    Abstract: No abstract text available
    Text: W M s LS190 - PRESETTABLE BCD/DECADE UP/DOWN COUNTERS LS191 - PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS 1 1 DESCRIPTION The T 54L S 190/T74LS 190 is a synchronous UP/DO W N BCD Decade 8421 Counter and the T54LS191/T74LS191 is a synchronous UP/DOW N Modulo-16 Binary Counter. State changes of the


    OCR Scan     		PDF LS190 LS191 190/T74LS T54LS191/T74LS191 Modulo-16 T54LS190/191 T74LS190/191

    Untitled

    Abstract: No abstract text available
    Text: s G S-THONSON 07E D | 7 ^ 2 3 7 D01b24S LOW POWER SCHOTTKY INTEGRATED CIRCUITS - 67 C 16374 D T-66-21-51 QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS DESCRIPTION ; The LSTTL/M SIT54LS258/258A , T74LS258/258A Is a Quad 2-Input Multiplexer with 3-state outputs.


    OCR Scan     		PDF D01b24S T-66-21-51 SIT54LS258/258A T74LS258/258A

    JT54LS

    Abstract: No abstract text available
    Text: S G S-THOrïSON D7E D g 7 1 2 T 2 3 7 LOW POWER SCHOTTKY INTEGRATED CIRCUITS _ 67C 1 55 12 T-5 Z-07 OCTAL BUFFER/LINË DRIVERS WITH 3-STATE OUTPUTS DESCRIPTIO N The T54LS/T74LS540/541 are Octal Buffers and Line Drivers. Although they have the same func­


    OCR Scan     		PDF T54LS/T74LS540/541 LS240 LS241, T74LSXXX T54LSXXX JT54LS

    LS126

    Abstract: ls125
    Text: a s LS125/125A - QUAD 3-STATE BUFFER LOW ENABLE LS126/126A - QUAD 3-STATE BUFFER (HIGH ENABLE) DESCRIPTION B1 Plastic Package The T54LS/T74LS125/125A/126/126A are high speed QUAD 3-STATE BUFFERS WITH ACTIVE HIGH ENABLES fabricated in LOW POWER SCHOTTKY tecnology.


    OCR Scan     		PDF LS125/125A LS126/126A T54LS/T74LS125/125A/126/126A T54LSXXXX T74LSXXXX LS125/125A LS126/126A LS126 ls125

    L5357

    Abstract: No abstract text available
    Text: S G S-THOMSON 07E D I 7 ^ 2 3 7 T54LS257/257A 1 T74LS257/257A OOlbEBö □ I LOW POWER SCHOTTKY 67C L5357 INTEGRATED CIRCUITS T-66-21-51 QUAD 2-IN P U T MULTIPLEXER W ITH 3-STA TE OUTPUTS DESCRIPTIO N The LSTTL/MSI T54LS257/257A, T74LS257/257A is a Quad 2-Input Multiplexer with 3-state outputs.


    OCR Scan     		PDF T54LS257/257A T74LS257/257A L5357 T-66-21-51 T54LS257/257A, T74LS257/257A L5357

    t114a

    Abstract: 1t4a T54LS/T74LS114/114A
    Text: S G K ? C m Î i S-THOnSON $ 1 ÎM 07E M D | 7^5^53? 0 UJi hü 31 4 | LOW POWER SCHOTTKY INTEGRATED CIRCUITS i l Ì T 7 4 L S t1 4 |M 67C 1 6 1 6 7 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS114/114A offer common clock and common clear inputs and individual J, K, and


    OCR Scan     		PDF T54LS/T74LS114/114A t114a 1t4a

    LS540

    Abstract: No abstract text available
    Text: PRELIMINARY DATA OCTAL BUFFER/LINE DRIVERS WITH 3-STATE OUTPUTS DESCRIPTION The T54LS/T74LS540/541 are Octal Buffers and Line Drivers. Although they have the same func­ tions as LS240 and LS241, they offer a pinout with inputs and outputs on apposite sides of the pac­


    OCR Scan     		PDF T54LS/T74LS540/541 LS240 LS241, T54LSXXX T74LSXXX LS540 LS541 LS540

    Untitled

    Abstract: No abstract text available
    Text: 4-STAGE PRESETTABLE RIPPLE COUNTERS DESCRIPTION The T54LS196/T74LS196 decade counter is par­ titioned into divide-by-two and divide-by-five sec­ tion which can be combined to count either in BCD 8 ,4,2 , 1 sequence or in a bi-quinary mode produ­ cing a 50% duty cycle output. The T54LS197/


    OCR Scan     		PDF T54LS196/T74LS196 T54LS197/ T74LS197 modulo-16

    BCD to 7 segment decoder with tails

    Abstract: LS247 LS248 74ls247 pin configuration 74LS247 18HM9
    Text: PRELIMINARY DATA BCD-TO-SEVEN-SEGMENT DECODER/DRIVES DESCRIPTION The T54LS/T74LS247/248 are BCD-to-seven seg­ ment Decoder/Drivers. They compose the and with the tails. The LS247 has active low outputs for di­ rect drive of indicators, while the LS248 has acti­


    OCR Scan     		PDF T54LS/T74LS247/248 LS247 LS248 Chi-10CVA T54LS/T74LS248) BCD to 7 segment decoder with tails 74ls247 pin configuration 74LS247 18HM9

    LS242

    Abstract: LS243
    Text: PRELIMINARY DATA QUAD BUS TRANSCEIVER DESCRIPTION T54LS/T74LS242/243 are high speed Quad Bus Transmitters/Receivers, intended for 4-line asyn­ chronous 2-way data communications between da­ ta buses. Each device has one active high enable E2 and one active low enble (E1). E2 enables the


    OCR Scan     		PDF T54LS/T74LS242/243 T54LSXXX T74LSXXX 1N306A LS242 LS243