RQW 130
Abstract: tlOH-tm33X ELLS 110 CY7C331
Text: i*bE ]> CYPRESS SEMICONDUCTOR B 256*^1.2 DDQ7Q5Q 7 Q C Y P c t 7C33i CYPRESS SEMICONDUCTOR Asynchronous Registered EPLD Features • Tnelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — O ne feedback flip-flop with input
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CT7C331
CY7C331-40QMB
CY7C331-40TMB
CY7C331-40WMB
DDQ7032
CY7C331
38-00066-C
RQW 130
tlOH-tm33X
ELLS 110
CY7C331
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TCO - 909 F 10 MHz
Abstract: TCO - 909 TCO - 909 F AN3131
Text: ^tco m AN3131 A N 3131 R F 3 > /< —^W Sk/ RF Converter Circuit • m m A N 3 1 3 1 Ü , SEC AM iÜi-tsSi l¡0 t so RF ^ > '• > '- 9 HJ U ? t i K t- m m m m -c -r , m 4# a • W lf£ '< ■■/ V 7- 7 > V r t i & s o / j s b S y n c . i f i ^ 'J ' ? I- >o
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AN3131
7AN3131
10/iF
400Hz
400Hz
TCO - 909 F 10 MHz
TCO - 909
TCO - 909 F
AN3131
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16L88
Abstract: PALC20 PALC16R6-20DMB cypress 16R4 PALC16L8-30DMB 16L8 16R4 16R6 16R8 PALC16R6-30DMB
Text: 256=^2 ooQb^o s d c y p MbE D CYPRESS SEMICONDUCTOR PAL C20 Series ~ SEMICONDUCTOR Features • CMOS EPROM technology for « p ro grammability • High performance at quarter power • — tpo = 25 ns — ts = 20 ns — tco = 15 ns — Ice = 45 mA • High performance at military
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PALC16R8L-35VC
PALC16R8L-35WC
PALC16R8â
PALC16R8-35PC/PI
PALC16R8-35VC/VC
PALC16R8-35WCAVC
PALC16R8-40DMB
PALC16R8-40KMB
PALC16R8-40LMB
PALC16R8-40QMB
16L88
PALC20
PALC16R6-20DMB
cypress 16R4
PALC16L8-30DMB
16L8
16R4
16R6
16R8
PALC16R6-30DMB
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12L10
Abstract: 16L6 20L10 20L8 PLD20G10C 12DC
Text: 4bE SEMICONDUCTOR SSÔTbtS D OGGbTMM PRELIMINARY CYPRESS SEMICONDUCTOR Features • Ultra high speed supports today’s and tomorrow’s fastest microprocessors — tpD = 7.5 ns — tsu = 3 ns — fM A X = 1 0 5 M tte • Reduced ground bounce and under
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PLD20G10C
24-Pin
10SMHZ
20L10,
12L10
PLD20G10C-
10KMB
10LMB
16L6
20L10
20L8
PLD20G10C 12DC
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Untitled
Abstract: No abstract text available
Text: Features • High Speed E le ctrica lly Erasable P rogram m able Lo g ic Device 7.5 ns Max Propagation Delay 5 V ±10% O peration Low Pow er ATF22V10BL -1 0 m A Standby CMOS and TTL C om patible In p uts and O utputs 150 nA Leakage M aximum R eprogram m able -100% Tested
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ATF22V10BL
ATF22V10B/L
250A-5A
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ma2837
Abstract: EPM1270 EPM2210 EPM240 EPM570
Text: Chapter 5. DC & Switching Characteristics MII51005-1.8 Operating Conditions Tables 5–1 through 5–12 provide information on absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for MAX II devices.
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MII51005-1
ma2837
EPM1270
EPM2210
EPM240
EPM570
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5M80Z
Abstract: 5M40Z 5M1270Z 5M2210Z 5M570Z 5M240Z 5M160Z max v 5m570z 5M1270 5M240
Text: 3. DC and Switching Characteristics for MAX V Devices May 2011 MV51003-1.2 MV51003-1.2 This chapter covers the electrical and switching characteristics for MAX V devices. Electrical characteristics include operating conditions and power consumptions. This
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MV51003-1
5M80Z
5M40Z
5M1270Z
5M2210Z
5M570Z
5M240Z
5M160Z
max v 5m570z
5M1270
5M240
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Untitled
Abstract: No abstract text available
Text: Features • A dvanced, H igh Speed P ro gram m ab le Logic Device Im proved P erform annce - 1 0 ns T p d , 100 M H z o peration E nhanced Logic Flexibility Backward C om patible w ith A TV 750/L S oftw are and H ardw are New Flip-Flop Features D- or T -Typ e
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750/L
24-Pin
24-Lead
28-Lead
248A-5
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MAX7064
Abstract: No abstract text available
Text: Chapter 5. DC and Switching Characteristics MII51005-2.2 Introduction System designers must consider the recommended DC and switching conditions discussed in this chapter to maintain the highest possible performance and reliability of the MAX II devices. This chapter contains
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MII51005-2
34Core
MAX7064
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356 schmitt trigger
Abstract: EPM1270 EPM2210 EPM240 EPM240Z EPM570
Text: 5. DC and Switching Characteristics MII51005-2.5 Introduction System designers must consider the recommended DC and switching conditions discussed in this chapter to maintain the highest possible performance and reliability of the MAX II devices. This chapter contains the following sections:
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MII51005-2
356 schmitt trigger
EPM1270
EPM2210
EPM240
EPM240Z
EPM570
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Untitled
Abstract: No abstract text available
Text: ZIL06 INC ^ S L blE D D E • cHfl4043 DGE5b2fl b33 « Z I L Pr o d u c t S p e c if ic a t io n Z16C30 CMOS USC UNIVERSAL SERIAL CONTROLLER FEATURES ■ Twoindependent,0to10Mbit/sec,fullduplexchannels. each with two baud rate generators and one digital phase-locked loop for clock recovery.
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ZIL06
Hfl4043
Z16C30
0to10Mbit/sec
32-byte
16-bit)
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eQFP 64 footprint
Abstract: eQFP 144 footprint 5M80Z 5M1270Z 5M240Z 5M40Z 5m240zt144 5M160z max v 5m 240z 5M80
Text: Section I. MAX V Device Core This section provides a complete overview of all features relating to the MAX V device family. This section includes the following chapters: May 2011 • Chapter 1, MAX V Device Family Overview ■ Chapter 2, MAX V Architecture
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MV51001-1
eQFP 64 footprint
eQFP 144 footprint
5M80Z
5M1270Z
5M240Z
5M40Z
5m240zt144
5M160z
max v 5m 240z
5M80
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intel 82576
Abstract: MLT 22 542 motherboard schematics diagram lga intel 945 motherboard schematic diagram foxconn 36 12f 575 Intel 82437 MOTHERBOARD pcb CIRCUIT diagram 686 8086 intel Programmers Reference Manual type w21 8222 - E
Text: Intel 82576 Gigabit Ethernet Controller Datasheet LAN Access Division LAD PRODUCT FEATURES Virtualization Ready External Interfaces PCIe* v2.0 (2.5 GT/s) x4/x2/x1; called PCIe in this document MDI (Copper) standard IEEE 802.3 Ethernet interface
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1000BASE-T,
100BASE-TX,
10BASE-T
1000BaseSX/X/LX
320961-015EN
intel 82576
MLT 22 542
motherboard schematics diagram lga
intel 945 motherboard schematic diagram
foxconn 36
12f 575
Intel 82437
MOTHERBOARD pcb CIRCUIT diagram 686
8086 intel Programmers Reference Manual
type w21 8222 - E
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Untitled
Abstract: No abstract text available
Text: CY14C256Q CY14B256Q CY14E256Q 256-Kbit 32 K x 8 SPI nvSRAM 256-Kbit (32 K × 8) SPI nvSRAM Features • ■ 256-Kbit nonvolatile static random access memory (nvSRAM) internally organized as 32 K × 8 ❐ STORE to QuantumTrap nonvolatile elements initiated
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CY14C256Q
CY14B256Q
CY14E256Q
256-Kbit
256-Kbit
CY14X256Q1A)
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Untitled
Abstract: No abstract text available
Text: CY14C512Q CY14B512Q CY14E512Q 512-Kbit 64 K x 8 SPI nvSRAM 512-Kbit (64 K × 8) SPI nvSRAM Features • ■ 512-Kbit nonvolatile static random access memory (nvSRAM) internally organized as 64 K × 8 ❐ STORE to QuantumTrap nonvolatile elements initiated
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CY14C512Q
CY14B512Q
CY14E512Q
512-Kbit
512-Kbit
CY14X512Q1A)
CY14C512Q:
CY14B512Q:
CY14E512Q:
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1048N6c
Abstract: trw tdc1048n6c 1048B6C RNE-64BS-S-TG TDC1048B6C DIN 41612B
Text: TDC1048 T R V w Monolithic Video A/D Converter 8-Bit, 20Msps The TRW TDC1048 is a 20 M sp s M egaSam ple Per Second full-parallel (flash) analog-to-digital converter, capable of converting an analog signal w ith fu ll-p o w e r frequency com ponents up to 7 M H z into 8 -b it digital
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TDC1048
20Msps
TDC1048
1048N6c
trw tdc1048n6c
1048B6C
RNE-64BS-S-TG
TDC1048B6C
DIN 41612B
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Untitled
Abstract: No abstract text available
Text: Section I. MAX II Device Family Data Sheet This section provides designers with the data sheet specifications for MAX II devices. The chapters contain feature definitions of the internal architecture, Joint Test Action Group JTAG and in-system programmability (ISP) information, DC operating conditions, AC timing
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Untitled
Abstract: No abstract text available
Text: Section I. MAX II Device Family Data Sheet This section provides designers with the data sheet specifications for MAX II devices. The chapters contain feature definitions of the internal architecture, Joint Test Action Group JTAG and in-system programmability (ISP) information, DC operating conditions, AC timing
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EPM240G
Abstract: EPM1270 EPM2210 EPM240 EPM570
Text: Section I. MAX II Device Family Data Sheet This section provides designers with the data sheet specifications for MAX II devices. The chapters contain feature definitions of the internal architecture, Joint Test Action Group JTAG and in-system programmability (ISP) information, DC operating conditions, AC timing
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ALTERA PART MARKING EPM
Abstract: EPM1270 EPM2210 EPM240 EPM240G EPM570
Text: Section I. MAX II Device Family Data Sheet This section provides designers with the data sheet specifications for MAX II devices. The chapters contain feature definitions of the internal architecture, Joint Test Action Group JTAG and in-system programmability (ISP) information, DC operating conditions, AC timing
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EPM570GT100C4
EPM570GT100I5
ALTERA PART MARKING EPM
EPM1270
EPM2210
EPM240
EPM240G
EPM570
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Untitled
Abstract: No abstract text available
Text: Intel 82576EB Gigabit Ethernet Controller Datasheet LAN Access Division LAD PRODUCT FEATURES Virtualization Ready External Interfaces PCIe* v2.0 (2.5 GT/s) x4/x2/x1; called PCIe in this document MDI (Copper) standard IEEE 802.3 Ethernet interface
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82576EB
1000BASE-T,
100BASE-TX,
10BASE-T
1000BaseSX/X/LX
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APM 7328
Abstract: yr92 SST25VF040A 82576NS RTL 8189 0x3a18 82576EB ms 7254 ver 1.1 INTEL application notes op amp 741 model hSpice
Text: Intel 82576EB Gigabit Ethernet Controller Datasheet LAN Access Division LAD PRODUCT FEATURES Virtualization Ready External Interfaces PCIe* v2.0 (2.5 GT/s) x4/x2/x1; called PCIe in this document MDI (Copper) standard IEEE 802.3 Ethernet interface
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82576EB
1000BASE-T,
100BASE-TX,
10BASE-T
1000BaseSX/X/LX
APM 7328
yr92
SST25VF040A
82576NS
RTL 8189
0x3a18
ms 7254 ver 1.1
INTEL application notes
op amp 741 model hSpice
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EPM570T144C5
Abstract: EPM240T100C5 EPM570T100C3 EPM240T100 EPM570T100C5
Text: Section I. MAX II Device Family Data Sheet This section provides designers with the data sheet specifications for MAX II devices. The chapters contain feature definitions of the internal architecture, Joint Test Action Group JTAG and in-system programmability (ISP) information, DC operating conditions, AC timing
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EPM1270F256C3
EPM1270
EPM1270F256C4
EPM1270F256C5
EPM1270T144C3
EPM1270T144C4
EPM1270T144C5
EPM1270*
EPM570T144C5
EPM240T100C5
EPM570T100C3
EPM240T100
EPM570T100C5
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EPM1270
Abstract: EPM2210 EPM240 EPM240G EPM570 full subtractor circuit using decoder MII51003-1
Text: Section I. MAX II Device Family Data Sheet This section provides designers with the data sheet specifications for MAX II devices. The chapters contain feature definitions of the internal architecture, Joint Test Action Group JTAG and in-system programmability (ISP) information, DC operating conditions, AC timing
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