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    TRISTATE BUFFER CMOS Search Results

    TRISTATE BUFFER CMOS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    54LS126A/BCA Rochester Electronics LLC 54LS126 - Quad bus buffer gates with Tristate Output - Dual marked (M38510/32302BCA) Visit Rochester Electronics LLC Buy
    74VHCT541AFT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, Octal Buffer, TSSOP20B Visit Toshiba Electronic Devices & Storage Corporation
    74VHC541FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, Octal Buffer, TSSOP20B Visit Toshiba Electronic Devices & Storage Corporation
    7UL1G125NX Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, XSON6, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL1G126NX Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, XSON6, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation

    TRISTATE BUFFER CMOS Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: AZP94 PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs www.azmicrotek.com FEATURES DESCRIPTION • Selectable Divide Ratio • Selectable Enable Polarity and Threshold CMOS or PECL • Tristate Compatible Outputs • Input Buffer Powers Down


    Original     		AZP94 AZP94 PDF

    AZP94

    Abstract: No abstract text available
    Text: AZP94 PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs www.azmicrotek.com FEATURES DESCRIPTION • Selectable Divide Ratio • Selectable Enable Polarity and Threshold CMOS or PECL • Tristate Compatible Outputs • Input Buffer Powers Down


    Original     		AZP94 AZP94 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54FCT244 54FCT244 Octal Buffer/Line Driver with -TRISTATE Outputs Literature Number: SNOS430 54FCT244 Octal Buffer/Line Driver with TRI-STATE Outputs General Description Features The ’FCT244 is an octal buffer and line driver with TRI-STATE outputs designed to be employed as a memory


    Original     		54FCT244 54FCT244 SNOS430 FCT244 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54FCT540 54FCT540 Octal Buffer/Line Driver with -TRISTATE Outputs Literature Number: SNOS431 54FCT540 Octal Buffer/Line Driver with TRI-STATE Outputs General Description Features The ’FCT540 is an octal buffer/line drivers designed to be employed as memory and address drivers, clock drivers and


    Original     		54FCT540 54FCT540 SNOS431 FCT540 FCT240 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54FCT541 54FCT541 Octal Buffer/Line Driver with -TRISTATE Outputs Literature Number: SNOS424 54FCT541 Octal Buffer/Line Driver with TRI-STATE Outputs General Description Features The ’FCT541 is an octal buffer and line driver with TRI-STATE outputs designed to be employed as a memory


    Original     		54FCT541 54FCT541 SNOS424 FCT541 FCT244 5962-8/clocks PDF

    Untitled

    Abstract: No abstract text available
    Text: 54FCT241 54FCT241 Octal Buffer/Line Driver with -TRISTATE Outputs Literature Number: SNOS425 54FCT241 Octal Buffer/Line Driver with TRI-STATE Outputs General Description Features The FCT241 is an octal buffer and line driver with 3-STATE outputs designed to be employed as a memory and address


    Original     		54FCT241 54FCT241 SNOS425 FCT241 54FCT241DMQB 54FCT241FMQB 54FCT241LMQB 20-Lead PDF

    Untitled

    Abstract: No abstract text available
    Text: PO11 ATL25 CMOS Gate Array cell data sheets 4.0 Description: Tristate output buffer, 2mA drive. Characterization: 25C, 3.3v, Nominal Process Cell area sites : 0.0 Pin caps(pF): AO=0.060, E0=0.060 Typical delay times (slope in ns/pF; intercept in ns; input transition = 0.600ns):


    Original     		ATL25 600ns) PDF

    PO22

    Abstract: PO-99 PO44 ATL35 PO33 PO55 CMOS GATE ARRAY AO40
    Text: PO11 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: Tristate output buffer, 2mA drive Truth Table: AO E0 PO11 E0 A0 E0 | P -X | Z 1 | 0 1 1 | 1 P E0 pchn2pad_x1 I1 AO AO gateP gateN outputDRVS1 I3 P I2 nchn2pad_x1 / $Revision: 1.35 $


    Original     		ATL35 25degC PO22 PO-99 PO44 PO33 PO55 CMOS GATE ARRAY AO40 PDF

    Untitled

    Abstract: No abstract text available
    Text: PO11 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: Tristate output buffer, 2mA drive Truth Table: AO E0 PO11 E0 A0 E0 | P -X | Z 1 | 0 1 1 | 1 P E0 pchn2pad_x1 I1 AO AO gateP gateN outputDRVS1 I3 P I2 nchn2pad_x1 / $Revision: 1.35 $


    Original     		ATL35 25degC PDF

    02-JUN

    Abstract: CS0897 sot665 74AUP1G125GTR 74AUP1G125 A115-A C101 74AUP
    Text: 74AUP1G125 Low power single tristate buffer Features • High speed: tPD = 6.3 ns max. at VCC = 2.3 V ■ Power down protection on inputs and outputs ■ Balanced propagation delays: tPLH ≈ tPHL ■ Operating voltage range: VCC (opr) = 1.2 to 3.6 V ■


    Original     		74AUP1G125 000-V A114-A) A115-A) OT-665 74AUP1G125 02-JUN CS0897 sot665 74AUP1G125GTR A115-A C101 74AUP PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AUP1G125 Low power single tristate buffer Features • High speed: tPD = 6.3 ns max. at VCC = 2.3 V ■ Power down protection on inputs and outputs ■ Balanced propagation delays: tPLH ≈ tPHL ■ Operating voltage range: VCC (opr) = 1.2 to 3.6 V ■


    Original     		74AUP1G125 000-V A114-A) A115-A) OT-665 74AUP1G125 PDF

    octal Bilateral Switches

    Abstract: MM74HC14M MM74HC138M CD4025BCM MM74HC00M MM74HC74AM MM74HC125M MM74HC04M cd4046bcm cd4052bcm
    Text: 1/3 CMOS LOGIC MM74HC SERIES MM74HCT/U SERIES • HIGH SPEED CMOS TECHNOLOGY, CMOS DRIVE LEVELS, SPEED COMPARABLE TO 74LS SERIES Part Number Description • HIGH SPEED CMOS TECHNOLOGY, TTL DRIVE LEVELS, SPEED COMPARABLE TO 74LS SERIES SQP £ ea. Gates & Inverters


    Original     		MM74HC MM74HC00M MM74HC02M MM74HC04M MM74HC08M MM74HC14M MM74HC32M MM74HC86M MM74HC132M MM74HC74AM octal Bilateral Switches MM74HC138M CD4025BCM MM74HC125M cd4046bcm cd4052bcm PDF

    TEMIC PLD

    Abstract: PRU10 PRD8 buffer 8x Structure of D flip-flop DFFSR AOI222 AOI2223 AOI2223H AOI222H MH1099
    Text: MH1 1.6 Million gates Sea of Gates / Embedded Arrays 1. Description The MH1 Series Gate Array and Embedded Array families from TEMIC are fabricated in a 0.35µ CMOS process, with up to 3 levels of metal. This family features arrays with up to 1.6 million routable gates and 600 pins. The


    Original     		PDF

    A/ATMEL 0843

    Abstract: No abstract text available
    Text: ATL80 - 0.8 µ I/O Buffer Cells Typical Delays at Tj = 25°C; Vdd = 5.0 V; Input Rise and Fall Times = 1 ns; Process = Nominal Sample of buffers composed of modular I/O building blocks Cell Name Description (Site Count) PBD2C 4 mA bidi CMOS buffer (1) PBD3C


    Original     		ATL80 PBD32TS A/ATMEL 0843 PDF

    T Flip-Flop

    Abstract: national hct 4049 datasheet 74 act 574 e hct 4049 datasheet TBA 240 a 4514 v 4049 CMOS Inverter 4049 schmitt trigger hc 4051 HC 123A
    Text: CMOS Logic KEY CMOS Logic Advanced CMOS FACT TM AC FACT Quiet Series TM (ACQ) FACT (ACT) FACT Quiet Series (ACTQ) FACT FCT VHC VHCT HC HCT T e available in JEDEC e e available in EIAJ Te e available in JEDEC and EIAJ w e available in wide format Tw e available in standard and


    Original     		MIL-STD-883 MIL-STD-883 T Flip-Flop national hct 4049 datasheet 74 act 574 e hct 4049 datasheet TBA 240 a 4514 v 4049 CMOS Inverter 4049 schmitt trigger hc 4051 HC 123A PDF

    AO4L

    Abstract: ld3p AO15A AO16A FD3S AO15AN AO23L BT8C datasheet MTC-35400 mux2*1
    Text: MTC-35000 CMOS 0.5µ Standard Cell Library Services October ‘98 CMOS Family Features • Technology - 0.5µ CMOS for mixed analog 2 digital application - 0.5 micron CMOS transistors, triple layer metal, single or doble poly layer - Self-aligned twin tub Nand P-wells


    Original     		MTC-35000 102ps 216ps AO4L ld3p AO15A AO16A FD3S AO15AN AO23L BT8C datasheet MTC-35400 mux2*1 PDF

    Untitled

    Abstract: No abstract text available
    Text: M T C -1 2 0 0 0 C M O S 1 .2 u Standard Cell Library Services CMOS Family Features • Technology: - 1.2 micron tw in -w ell CMOS process w ith polycide gates, double layer m etal, linear Ihin oxide capacitors and high ohmic resistors - Shrink capability to


    OCR Scan     		BHDA08A BHAD12A BHSD14A PDF

    Tri-State Buffer CMOS

    Abstract: tristate buffer cmos tristate buffer active low 5962R9577201VXC Advanced TTL Logic ACS244MS ACS541MS HCTS240ADMSR HCTS240AHMSR HCTS240AKMSR
    Text: HCTS240AMS Device Information Printer Friendly Version HCTS240AMS Driver, Buffer/Line, Inverter, Tri-State, TTL Inputs, Octal, Rad-Hard, High-Speed, CMOS, Logic Get Datasheet Ordering Information Price Status Temp. Package MSL SMD US $ 20 Ld Contact HCTS240ADMSR Active N/A 5962R9577201VRC


    Original     		HCTS240AMS HCTS240AMS HCTS240ADMSR 5962R9577201VRC HCTS240AHMSR HCTS240AKMSR 5962R9577201VXC J-STD-020 Tri-State Buffer CMOS tristate buffer cmos tristate buffer active low 5962R9577201VXC Advanced TTL Logic ACS244MS ACS541MS PDF

    Untitled

    Abstract: No abstract text available
    Text: M T C - 2 2 0 0 0 C M O S 0 .7 n Standard Cell Family Services CMOS Family Features • Technology: CMOS 0 .7 m icron, double or triple la y e r m etal digital or m ix e d a n a lo g /d ig ita l processes, featu rin g self­ aligned tw in tub N an d P w ells, polycide or polysilicon


    OCR Scan     		I08CR 08SCR PDF

    16-LINE TO 4-LINE PRIORITY ENCODERS

    Abstract: 32-Bit Parallel-IN Serial-OUT Shift Register RS flip flop cmos 16-to-4 line priority encoder RS flip flop DSTD190 CMOS Quad 2-Input NOR Gate encoder 74174 jk flip flop to d flip flop conversion T Flip-Flop
    Text: CMOS PLD Designing with the Atmel-ViewPLD Development Tool Like the Atmel-ABEL software, the Atmel-ViewPLD development tool uses a popular industry-standard CAE development system. The development tool integrates the Viewlogic Workview software as the design environment with Data I/O’s


    Original     		thD882 32-Bit DSTD90 DSTD91 DSTD92 Divide-by-12 DSTD93 DSTD94 ATV5000 ATV5100 16-LINE TO 4-LINE PRIORITY ENCODERS 32-Bit Parallel-IN Serial-OUT Shift Register RS flip flop cmos 16-to-4 line priority encoder RS flip flop DSTD190 CMOS Quad 2-Input NOR Gate encoder 74174 jk flip flop to d flip flop conversion T Flip-Flop PDF

    208-pin cpga

    Abstract: No abstract text available
    Text: Military 5.0V pASIC 1 Family Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA last updated 5/15/2000 Military 5.0V pASIC 1 Family DEVICE HIGHLIGHTS FEATURES Device Highlights Features Very High Speed • ViaLink“ metal-to-metal programmable technology, allows counter speeds over 150 MHz and


    Original     		24-by-32 208-pin 24x32B CF208 M/883C 8x12B 12x16B 16x24B 208-pin cpga PDF

    68-PIN

    Abstract: 84-PIN cpga pinout 208-pin cpga
    Text: Military 5.0V pASIC 1 Family Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA Military 5.0V pASIC 1 Family DEVICE HIGHLIGHTS FEATURES Device Highlights Features Very High Speed • ViaLink“ metal-to-metal programmable technology, allows counter speeds over 150 MHz and


    Original     		24x32B CF208 M/883C 8x12B 12x16B 16x24B 24x32B 68-pin 84-pin CG144 cpga pinout 208-pin cpga PDF

    Untitled

    Abstract: No abstract text available
    Text: MM54HCT540/MM74HCT540 Inverting Octal TRI-STATE Buffer MM54HCT541/MM74HCT541 Octal TRI-STATE Buffer General Description These TRI-STATE buffers utilize advanced silicon-gate CMOS technology and are general purpose high speed in­ verting and non-inverting buffers. They possess high drive


    OCR Scan     		MM54HCT540/MM74HCT540 MM54HCT541/MM74HCT541 MM54HCT/MM74HCT PDF

    HXE12

    Abstract: AMI500HXPF
    Text: 0.5 Micron CMOS Pad Library Datasheets AMI500HXPF 5.0 Volt Section 4 Revision 1.1 Selection Guide AMI500HXPF 0.5 micron CMOS Pad Library PAD SELECTION GUIDE Input Drive Pieces Name Description IDCI3 IDCR0 IDCS3 IDCXx IDPX3 IDQC0 IDQC3 IDQS3 IDTS3 IDTXx Inverting, CMOS-level input buffer piece .4-5


    Original     		AMI500HXPF HXE12 PDF