cwI 1011
Abstract: No abstract text available
Text: 5 > H A K P LH52D08S 1 Contents 1. Description . . 2 . 2. Pin Configuration 2 3. Truth Table 3 4. Block Diagram . . . . . . . . 5. Absolute Maximum Ratings
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LH52D08S
G1S7C14
cwI 1011
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2516 rom
Abstract: No abstract text available
Text: 2516-N.I TRUTH TABLE PIN CONFIGURATION f f l O R I C f DESCRIPTION AC TEST SETUP f f l C TIMING DIAGRAM t* * u CHARACTER ADDRESS/ 1 V, COLUMN ADDRESS «A,-A3> *o 2'T , r aov f\ I i V o .w X » . ; : / “ V P A » v _ 55 ' r ^ - lC L A - ^ CHARACTER FORMAT
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2516-N
6G6GG6666666G666GGG66B66666666666GG66GS6G
2516 rom
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Untitled
Abstract: No abstract text available
Text: U f Optical Encoders CIRCUITRY, TRUTH TABLE, AND WAVEFORM Standard Quadrature 2-Bit Code OUTPUT A HIGH LOW V \ & HIGH OUTPUT B LOW / i i i i 1 2 3 4 \ i i 5 6 C lockw ise R otation P osition j POSITION NUMBfcR O utput A O utpu t B 1 2 • 3 • 4 • • • Indicates logic high; blank indicates
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74LS137
Abstract: No abstract text available
Text: MOTOROLA < 8 > V CC D A T A O U TP U TS _ A _ Y3 Y4 / Y0 Y1 Y2 YO Y1 Y2 Y3 SN54LS137 SN74LS137 Y5 Y4 Y6 N 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES Y5 TTTT LOW POWER SCHOTTKY LU LU üJ'Lll Li] LU, LzJ l£j , A B 'V ” C / VGL S I V" G1
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SN54LS137
SN74LS137
74LS137
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74LS137
Abstract: No abstract text available
Text: <8> MOTOROLA SN54/74LS137 D A T A O U T PU T S V CC / Y0 Y1 f61 £¡1 Fyi YO Y2 Y3 Y4 FI R I YS Y6 ^ FH R Y1 Y2 Y3 Y4 Y5 C GL 53 GJ Y7 A fT | 3-UNE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES Y6 B TTTTTT “ V" SELECT Cy x 6 l 53 G îy LOW POWER SC HO TTK Y
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SN54/74LS137
74LS137
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Untitled
Abstract: No abstract text available
Text: M OTOROLA SN54LS266 SN74LS266 R R R R R R f7! TRUTH TA BLE IN OUT A B Z L L H L H L H L L H H H QUAD 2-INPUT EXCLUSIVE NOR GATE LOW POWER SCHOTTKY TTTinirTinirMTir •O PE N COLLECTOR OUTPUTS J Suffix — Case 632-07 Ceramic N Suffix — Case 646-05 (Plastic)
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SN54LS266
SN74LS266
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Untitled
Abstract: No abstract text available
Text: æ HD-4702/883 HARRIS S E M I C O N D U C T O R CMOS Programmable Bit Rate Generator August 1996 Description Features • The HD-4702/883 Bit Rate Generator provides the neces sary clock signals for digital data transmission systems, such as a UART. It generates 13 commonly used bit rates using
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HD-4702/883
HD-4702/883
4576M
MIL-STD883
Samples/5005
100kHz
10ki2,
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Untitled
Abstract: No abstract text available
Text: D C So lid S ta te R elay SHORT CIRCUIT PROTECTED, TRUE OUTPUT STATUS FEEDBACK, 2A, 60 Vdc TTTELEDYNE RELAYS Part* Number DESC Drawing Relay Description Number HDOOCFW HDOOCFY Solid State Relay SSR 88062-008 SSR with Switch Status HD02CFW HD02CFY SSR with Short Circuit Protection
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HD02CFW
HD02CFY
HD22CFW
HD22CFY
HD20CFW
HD20CFY
HD24CFW
HD24CFY
MIL-R-28750
DC-12
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dm024
Abstract: A992 transistor and its equivalent LB 11917
Text: LOGIC LEA300K Embedded Array 5 Volt ASIC Products Databook O c to b e r 1994 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.
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LEA300K
DB04-000048-00,
D-102
FALU32
32-bit
FMPY32
FALU32P
dm024
A992 transistor and its equivalent
LB 11917
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IC 74LS47
Abstract: pin diagram of 74LS47 TTL IC 74ls470 motorola 74ls47 74LS47 7-segment 74ls47 74LS47 functions 74LS47 gate diagram 74LS47 pin ic 74ls47 and 7 segment
Text: g MOTOROLA SN54/74LS47 BCD TO 7-SEGMENT DECODER/DRIVER The S N 54/74LS 47 are Low Power Schottky BCD to 7-Segment Decod er/D rivers consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. They offer active LOW, high sink current outputs for driving
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SN54/74LS47
54/74LS
IC 74LS47
pin diagram of 74LS47 TTL IC
74ls470
motorola 74ls47
74LS47
7-segment 74ls47
74LS47 functions
74LS47 gate diagram
74LS47 pin
ic 74ls47 and 7 segment
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DIGITAL GATE EMULATOR USING 8085
Abstract: 8086 microprocessor book by A K RAY 180 nm CMOS standard cell library AMI IC1732 DL021 M91C360 ami 0.6 micron 3682D ami equivalent gates ic/TDA7388 equivalent
Text: Library Characteristics il A M I AMERICAN MICROSYSTEMS, INC. L ib ra ry Characteristics AMI6G 0.6 micron CMOS Gate Array AMI6Gx Gate Array Family Overview U S A B LE G ATES1 PART NUM B ER2 B O N D PAD S I/O C E L L S 2 LM 3 LM AMI6G4 1.39 1.85 44 52 AMI6G16S
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AMI6G16S
AMI6G33S
AMI6G41S
AMI6G70S
AMI6G106S
AMI6G150S
AMI6G202S
AMI6G333
AMI6G471
AMI6G603
DIGITAL GATE EMULATOR USING 8085
8086 microprocessor book by A K RAY
180 nm CMOS standard cell library AMI
IC1732
DL021
M91C360
ami 0.6 micron
3682D
ami equivalent gates
ic/TDA7388 equivalent
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MB81116420
Abstract: No abstract text available
Text: July 1994 Edition 4.0 FUJITSU DATA SHEET MB81116820-010/-012/-015 CMOS 2 X 1 M X 8 SYNCHRONOUS DRAM CMOS 2 BANKS OF 1,048,576-WORDS x 8-BIT SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY The Fujitsu MB81116820 is a CMOS Synchronous Dynamic Random Access Memory SDRAM containing 16,777,216 memory cells accessible in an 8-bit format. The
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MB81116820-010/-012/-015
576-WORDS
MB81116820
MB81116420
44-LEAD
FPT-44P-M10)
F44015S-1C-1
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motorola 74ls47
Abstract: 74LS47 ttl 74ls47 74LS47 functions ttl 74ls47 7 segment LS 74LS47 of 74ls47 7-segment 74ls47 74LS47 pin configuration 74LS47 pin
Text: g MOTOROLA SN54/74LS47 BCD TO 7-SEGMENT DECODER/DRIVER The S N 54/74LS 47 are Low Power Schottky BCD to 7-Segment Decod er/D rivers consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. They offer active LOW, high sink current outputs for driving
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SN54/74LS47
motorola 74ls47
74LS47
ttl 74ls47
74LS47 functions
ttl 74ls47 7 segment
LS 74LS47
of 74ls47
7-segment 74ls47
74LS47 pin configuration
74LS47 pin
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Gray to excess-3 code conversion
Abstract: Excess-3-gray code Excess-3-gray code to Decimal decoder Excess-3-gray decoder Excess-3-gray Gray to excess-3 7444 Excess-3-gray code to Decimal decoder S5444W N7444F N7444N
Text: LOGIC SYMBOL 54/7444 15 DESCRIPTION a 14 a 13 ., a 12 2 3 a The “ 44 " is a TTL MSI array utilized in de coding and logic conversion applications. The “ 4 4 ” d e codes e x c e s s -th re e -g ra y code to 1 -o f - 1 0 outputs. 1 2 3 4 5 6 7 8 9 TTTTTTTTTT
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1-of-10
N7444N
N7444F
S5444F
S5444W
54S/74S
54LS/74LS
400S2
Gray to excess-3 code conversion
Excess-3-gray code
Excess-3-gray code to Decimal decoder
Excess-3-gray decoder
Excess-3-gray
Gray to excess-3
7444 Excess-3-gray code to Decimal decoder
S5444W
N7444N
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Untitled
Abstract: No abstract text available
Text: KM736V795 128Kx36 Synchronous SRAM 128Kx36-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2 Stage Pipelined operation with 4 Buret. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers.
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KM736V795
100-TQFP-1420A
128Kx36
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S42A
Abstract: No abstract text available
Text: M MOTOROLA. M ilita ry 54L S 42A 1-of-10 D ecoder hg&d MPO mini ELECTRICALLY TESTED PER: MIL-M-38510/30703 The LSTTL/MSI 54LS42A is a multipurpose decoder designed to accept four BCD inputs and provide ten mutually exclusive outputs. The LS42A is fabricated with the Schottky barrier diode process for
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1-of-10
MIL-M-38510/30703
54LS42A
LS42A
JM38510/30703BXA
54LS42A/BXAJC
S42A
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jk 13001 TRANSISTOR
Abstract: jk 13001 13001 S 6D TRANSISTOR jk 13001 h signo 723 operation manual jk 13001 E bd4 lsi logic 0 281 020 099 SIS transistors 13001 s bd 13001 S 6D TRANSISTOR circuit
Text: LSI LOGIC LCA500K Prelim inary D esig n M anual June 1995 S304 A0 4 O O n s t M h3? This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.
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LCA500K
043/G
LCA500K
jk 13001 TRANSISTOR
jk 13001
13001 S 6D TRANSISTOR
jk 13001 h
signo 723 operation manual
jk 13001 E
bd4 lsi logic
0 281 020 099 SIS
transistors 13001 s bd
13001 S 6D TRANSISTOR circuit
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qml-38535
Abstract: 54F109 CQCC1-N20 GDFP2-F16 GDIP1-T16
Text: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED REV SHEET REV SHEET 15 REV STATUS OF SHEETS PMIC N/A REV SHEET 1 2 4 3 PREPARED BY RICK OFFICER STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY 32K x 32 Pipelined Burst SRAM +3.3 V Supply, Fully Registered Inputs, Outputs, and Burst Counter FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 8 and 9 ns The Sharp Synchronous SRAM family employs high speed, low-power CMOS designs using a thin-film tran
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100-pin
DES10.
LH51V1032
LH51V1032C4
100TQFP
TQFP-1OO-P-1420)
LH51V1032C4
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Untitled
Abstract: No abstract text available
Text: Reversible-motor driver BA6285FS BA6285FP The BA6285FS and the BA6285FP are reversible motor drivers suitable for single motors. Dimensions Units : mm BA6285FS (SSOP-A16) Features b . t j KJ . / • available in SSOP-A16 and HSOP24 packages • supply voltage range (4.5 to 15 V)
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BA6285FS
BA6285FP
BA6285FP
SSOP-A16
HSOP24
BA6285FS)
BA6285FP)
BA6285FS,
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74LS115
Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
Text: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con necting first darlington emitter to output should have series resistor. LS33 5-25
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Untitled
Abstract: No abstract text available
Text: european space agency agence spatiale européenne Pages 1 to 66 INTEGRATED CIRCUITS, SILICON MONOLITHIC, CMOS SILICON GATE, STATIC 9K 1024x9 BIT FIRST IN, FIRST OUT MEMORY WITH 3-STATE OUTPUTS, BASED ON TYPE M67202FV ESA/SCC Detail Specification No. 9301/032
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1024x9
M67202FV
CKBD-000
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qml-38535
Abstract: 54ACQ245 CQCC1-N20 GDFP2-F20
Text: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED 98-11-05 Monica L. Poelklng Change limits for V o l . Editorial changes throughout - jak. REV SHEET REV A A A A SHEET 15 16 17 18 REV STATUS OF SHEETS PM 1C N/A REV A A A A A A A A A A A SHEET 1 2 3 4 5 6
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T00470Ã
qml-38535
54ACQ245
CQCC1-N20
GDFP2-F20
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Untitled
Abstract: No abstract text available
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 16K x 15 Bit Cache Tag RAM for PowerPC Processors The MPC27T415 is a 245,760 bit cache-tag static RAM designed to support PowerPC microprocessors at bus speeds up to 66 MHz. It is organized as 16K words of 15 bits each. There are 12 common I/O tag bits and 3 separate I/O status
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MPC27T415
12-bit
27T415
MPC27T415TQ9
MPC27T41STQ9R
MPC27T415TQ10
MPC27T41STQ1
MPC27T415TQ12
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