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    TSOP 48 PIN TRAY Search Results

    TSOP 48 PIN TRAY Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CS-DSDMDB09MF-010 Amphenol Cables on Demand Amphenol CS-DSDMDB09MF-010 9-Pin (DB9) Deluxe D-Sub Cable - Copper Shielded - Male / Female 10ft Datasheet
    CS-DSDMDB15MF-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB15MF-002.5 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Female 2.5ft Datasheet
    CS-DSDMDB15MM-025 Amphenol Cables on Demand Amphenol CS-DSDMDB15MM-025 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Male 25ft Datasheet
    CS-DSDMDB25MM-010 Amphenol Cables on Demand Amphenol CS-DSDMDB25MM-010 25-Pin (DB25) Deluxe D-Sub Cable - Copper Shielded - Male / Male 10ft Datasheet
    CS-DSDMDB37MM-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB37MM-002.5 37-Pin (DB37) Deluxe D-Sub Cable - Copper Shielded - Male / Male 2.5ft Datasheet

    TSOP 48 PIN TRAY Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    48-pin TSOP I

    Abstract: No abstract text available
    Text: Packing Name JEDEC Tray TSOP I 12x20 48 pin TSOP (I) (12 × 20) detail of lead end 1 48 F G R Q 24 L 25 S E P I A J C S K N S NOTES 1) Controlling dimension 3) "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX. <0.489 inch MAX.>) EIAJ CODE Weight (Reference Value)


    Original     		S48GZ-50-MJH 48-pin TSOP I PDF

    48-pin TSOP I

    Abstract: tray tsop 1220 JEDEC TRAY
    Text: Packing Name JEDEC Tray TSOP I 12x20 48 pin TSOP (I) (12 × 20) detail of lead end 1 48 E S L Q R 24 G 25 F K N M M D S S I B C J A P NOTES 1) Controlling dimension ITEM Millimeter. 2) Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.


    Original     		S48GZ-50-MKH 48-pin TSOP I tray tsop 1220 JEDEC TRAY PDF

    TSOP 48 package tray

    Abstract: 48-pin TSOP package tray tsop 48 PIN tray TSOP package tray TSOP I JEDEC TRAY DIMENSIONS TRAY TSOP
    Text: 150° MAX. 14.90 A 8x12=96 15.80 104.3 TSOP I 12.0×20.0mm A' 12.3 20.3 25.50 17.25 280.5 315.0 322.6 SECTION A – A' 5.62 (6.35) 20.3 7.62 135.9 UNIT : mm Applied Package Quantity (pcs) 48-pin Plastic TSOP (I) (12×20) MAX. 96 Tray Material Heat Proof Temp.


    Original     		48-pin TSOP 48 package tray 48-pin TSOP package tray tsop 48 PIN tray TSOP package tray TSOP I JEDEC TRAY DIMENSIONS TRAY TSOP PDF

    TSOP 48 package tray

    Abstract: 48-pin TSOP package tray tsop 48 PIN tray JEDEC tray standard TSOP package tray tsop TRAY TSOP TRAY 40 PIN
    Text: TRAY CONTAINER UNIT : mm 8x13=104 NEC 7 135°C MAX. 14.90 15.80 A' 23.50 12.10 104.3 TSOP 1 12×18 135.9 PPE A 18.40 282.0 315.0 (322.6) 16.50 SECTION A – A' 5.62 (6.35) 7.62 18.40 Applied Package Quantity (pcs) 48-pin Plastic TSOP (I) (12 × 18) MAX. 104


    Original     		48-pin SSD-A-H6761 TSOP 48 package tray 48-pin TSOP package tray tsop 48 PIN tray JEDEC tray standard TSOP package tray tsop TRAY TSOP TRAY 40 PIN PDF

    48-pin TSOP I

    Abstract: S48GY-50-MJH1
    Text: Packing NEC Tray Name LA-2503B-1 48 pin TSOP I (12 x 18) 1 detail of lead end 48 F G R Q 24 L 25 S E P I A J C S K N S NOTES Millimeter. 2. Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.


    Original     		LA-2503B-1 S48GY-50-MJH1 48-pin TSOP I S48GY-50-MJH1 PDF

    A6 TSOP-6 MARKING

    Abstract: No abstract text available
    Text: S29AL016D 16 Megabit 2 M x 8-Bit/1 M x 16-Bit CMOS 3.0 Volt-only Boot Sector Flash Memory Datasheet ADVANCE INFORMATION Distinctive Characteristics Architectural Advantages Package Options „ Single power supply operation „ 48-ball FBGA „ 48-pin TSOP — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications


    Original     		S29AL016D 16-Bit) 48-ball 48-pin 200nm Am29LV160D MBM29LV160E S29AL016D A6 TSOP-6 MARKING PDF

    NEC A39A

    Abstract: No abstract text available
    Text: Packing Name Mounting Pad NEC Tray LA-A39A 48 pin TSOP II (550 mil) 48 25 +4° E 2° –2° F detail of lead end 1 24 A J K G H I C D N B L M M S48G8-80-7JF-1 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at


    Original     		LA-A39A S48G8-80-7JF-1 NEC A39A PDF

    NEC A39A

    Abstract: transistor a39a
    Text: Mounting Pad Packing Name NEC Tray LA-A39A 48 pin TSOP II (550 mil) 48 25 F E 2° –2° +4° detail of lead end 1 24 A M M D N L B G K C I J H S48G8-80-7KF-1 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at


    Original     		LA-A39A S48G8-80-7KF-1 NEC A39A transistor a39a PDF

    S48GY-50-MJH-3

    Abstract: 48-pin TSOP I la 25-p
    Text: Mounting Pad Packing NEC Tray Name LA-2503B-1 48 pin TSOP I (12 x 18) 1 48 detail of lead end S R Q 24 25 P I J H S A G C B L N S D K NOTES M M ITEM 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition.


    Original     		LA-2503B-1 SC-668 S48GY-50-MJH-3 S48GY-50-MJH-3 48-pin TSOP I la 25-p PDF

    48-pin TSOP I

    Abstract: No abstract text available
    Text: Packing NEC Tray Name LA-2503B-1 48 pin TSOP I (12 x 18) 1 detail of lead end 48 E S Q L R 24 G 25 F K N S M M D S I B C J A P NOTES ITEM 1. Controlling dimension Millimeter. 2. Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.


    Original     		LA-2503B-1 S48GY-50-MKH1 48-pin TSOP I PDF

    48-pin TSOP I

    Abstract: S48GY-50-MKH-3
    Text: Mounting Pad Packing NEC Tray Name LA-2503B-1 48 pin TSOP I (12 x 18) 1 48 detail of lead end Q 24 S 25 N K H D S L R M M B C S I J G A P NOTES ITEM 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition.


    Original     		LA-2503B-1 SC-668 S48GY-50-MKH-3 48-pin TSOP I S48GY-50-MKH-3 PDF

    48-pin TSOP package tray

    Abstract: TSOP 48 package tray tsop 48 PIN tray
    Text: TRAY CONTAINER Unit : mm 335±1.0 23.5±0.5 288±0.5 21.25±0.5 137.5±0.5 180±1.0 27.5±0.1 32±0.1 18.3 A' NEC LA-2503B-1 HEAT PROOF A 15.5 SECTION A – A' 18.3 6.3 5.8 8.8 15 Applied Package Quantity pcs 48-pin Plastic TSOP (I) (12x18) MAX. 60 Tray


    Original     		LA-2503B-1 48-pin SSD-A-H5743 48-pin TSOP package tray TSOP 48 package tray tsop 48 PIN tray PDF

    48-pin TSOP package tray

    Abstract: TSOP 48 package tray tsop 48 PIN tray
    Text: Unit : mm 335±1.0 23.5±0.5 288±0.5 21.25±0.5 137.5±0.5 180±1.0 27.5±0.1 32±0.1 18.3 A' NEC LA-2503B-1 HEAT PROOF A 15.5 SECTION A – A' 18.3 6.3 5.8 8.8 15 Applied Package Quantity pcs 48-pin Plastic TSOP (I) (12x18) MAX. 60 Tray LA-2503B-1 Material


    Original     		LA-2503B-1 48-pin 48-pin TSOP package tray TSOP 48 package tray tsop 48 PIN tray PDF

    Untitled

    Abstract: No abstract text available
    Text:  LY62L25716 256K X 16 BIT LOW POWER CMOS SRAM Rev. 2.5 REVISION HISTORY Revision Rev. 1.0 Rev. 2.0 Rev. 2.1 Rev. 2.2 Rev. 2.3 Rev. 2.4 Rev. 2.5 Description Initial Issue Revised ISB max : 0.5mA => 1.25mA Adding 44-pin TSOP-II Adding 48-ball BGA Revised IDR


    Original     		LY62L25716 44-pin 48-ball 48-pin PDF

    JEDEC TRAY DIMENSIONS

    Abstract: TSOP 8x14 TSOP 48 package tray TSOP 32ld tray JEDEC TRAY 10 X 10 shipping tray jedec tray scale TSOP package tray
    Text: _L _L _L 001IHAL RELEASE. NOTE : 1. BAKEABLE TRAYS ARE INTENDED TO BE CONTINUOUSLY BAKED FOR 48 HOURS AT THE BAKE TEMPERATURE AS SPECIFIED. 2. TOTAL USABLE CELL COUNT IS 208. 3. TRAY VACUUM PICKUP METHOD REQUIRES A 28m m SQUARE MINIMUM WALLED PICKUP AREA , LOCATED AS CLOSE TO


    OCR Scan     		001IHAL 1X105 1X1012 JEDEC TRAY DIMENSIONS TSOP 8x14 TSOP 48 package tray TSOP 32ld tray JEDEC TRAY 10 X 10 shipping tray jedec tray scale TSOP package tray PDF

    MD300-10A

    Abstract: QFN tray tray datasheet bga SIP 400B TSOP TRAY 40 PIN BGA package tray 64 NEC A39A 240 TSOP package tray 6-tsop TRAY DIMENSIONS 132 PGA
    Text: CHAPTER 4 CHAPTER 4 4.1 PACKING STYLES AND NOTES 4.1.1 Packing Styles 4.1.2 Notes on Handling 4.2 PACKING OF IC PACKAGES 4.2.1 List of Packing 1 DIP (2) SIP, V-DIP, ZIP (3) QUIP, Piggyback (4) PGA (5) SOP, SSOP (6) TSOP (I) (II) (7) QFP, QFP (FP) (8) SVP


    Original     		S64F1-CA1 S108S1-YHC P116S1-YJC S144S1-YKC S176S1-2C S224S1-3C-1 S304S1-6C S256N7-B6 S352N7-F6-1 S420N7-F6 MD300-10A QFN tray tray datasheet bga SIP 400B TSOP TRAY 40 PIN BGA package tray 64 NEC A39A 240 TSOP package tray 6-tsop TRAY DIMENSIONS 132 PGA PDF

    AMD AM28F010 ca

    Abstract: AM29 flash 48-pin TSOP package tray tsop 48 PIN SOCKET pin identification AMD 2m flash memory Meritec Am29LV033B AM29F010 Am29F002N AM29F002
    Text: Flash Memory Quick Reference Guide Summer ’98 Package Migration Low-Voltage Am29LV004 Am29LV008B Am29LV081 Am29LV116B Am29LV017B 2 Mb 4 Mb 8 Mb 16 Mb Am29LV010B Am29LV001B Am29LV020B Am29LV102B Am29LV040B Am29LV104B 1 Mb 2 Mb 4 Mb Am29LV200 Am29DL400B Am29LV400


    Original     		Am29LV004 Am29LV008B Am29LV081 Am29LV116B Am29LV017B Am29LV010B Am29LV001B Am29LV020B Am29LV102B Am29LV040B AMD AM28F010 ca AM29 flash 48-pin TSOP package tray tsop 48 PIN SOCKET pin identification AMD 2m flash memory Meritec Am29LV033B AM29F010 Am29F002N AM29F002 PDF

    HN58V1001TI-25E

    Abstract: R1EX25256ATA00I renesas tcam tcam renesas cypress tcam idt tcam r1qaa7218rbg R1LV0816A M5M51008DFP-55H R1LV1616RBG-7SI
    Text: 2009.04 Renesas General-Purpose Memory General Catalog www.renesas.com Highly Reliable Technological Innovation Ever faster, ever more power efficient…. Our advanced technology delivers To give your products the edge in today’s tough competitive higher quality and reliability,


    Original     		REJ01C0001-1000 HN58V1001TI-25E R1EX25256ATA00I renesas tcam tcam renesas cypress tcam idt tcam r1qaa7218rbg R1LV0816A M5M51008DFP-55H R1LV1616RBG-7SI PDF

    tsop tray matrix outline

    Abstract: tsop Shipping Trays JEDEC Matrix Tray outlines Atmel 918 EIA-481-x ATMEL Packing Methods and Quantities JEDEC Matrix Tray outlines soic ATMEL Tape and Reel PLCC JEDEC tray Shipping Trays
    Text: Packages Available Packing Methods and Quantities Atmel provides four different packing methods to provide maximum protection for our product and to best suit our customer’s needs: 1 Shipping Tubes, 2) Shipping Trays, 3) Unit Packing, and 4) Tape and Reel. These first three methods are our standard pack, but we also


    Original     		PDF

    NEC A39A

    Abstract: NEC A39A 240 SOP28 330 mil land pattern NEC A39A 8 PIN mjh 106 120-PIN 282 185 01 smd TRANSISTOR code b6 ED-7500 transistor a39a SIP 400B
    Text: IC PACKAGE MANUAL 1991, 1992, 1994, 1996 Document No. C10943XJ6V0IF00 Previous No. IEI-635, IEI-1213 Date Published January 1996 P Printed in Japan CHAPTER 1 PACKAGE OUTLINES AND EXPLANATION CHAPTER 2 CHAPTER 3 1 THROUGH HOLE PACKAGES 2 SURFACE MOUNT PACKAGES


    Original     		C10943XJ6V0IF00 IEI-635, IEI-1213) ED-7411 NEC A39A NEC A39A 240 SOP28 330 mil land pattern NEC A39A 8 PIN mjh 106 120-PIN 282 185 01 smd TRANSISTOR code b6 ED-7500 transistor a39a SIP 400B PDF

    28 TSSOP JEDEC Thin Matrix Tray outlines

    Abstract: tsop tray matrix outline Shipping Trays ATMEL Packing Methods and Quantities ATMEL EIA-481-x Packing ATMEL 234 tsop Shipping Trays atmel tape and reel JEDEC Matrix Tray outlines EIA-481-x
    Text: Available Packing Methods and Quantities Atmel provides four different packing methods to provide maximum protection for our product and to best suit our customer’s needs: 1 Shipping Tubes, 2) Shipping Trays, 3) Unit Packing, and 4) Tape and Reel. These first three


    Original     		0637D 09/99/xM 28 TSSOP JEDEC Thin Matrix Tray outlines tsop tray matrix outline Shipping Trays ATMEL Packing Methods and Quantities ATMEL EIA-481-x Packing ATMEL 234 tsop Shipping Trays atmel tape and reel JEDEC Matrix Tray outlines EIA-481-x PDF

    LGA 1156 PIN OUT diagram

    Abstract: QSJ-44403 LGA 1150 Socket PIN diagram LGA 1155 Socket PIN diagram IC107-26035-20-G LGA 1151 PIN diagram REFLOW lga socket 1155 IC107-3204-G TB 2929 H alternative LGA 1155 pin diagram
    Text: DIP8-P-300-2.54 5 Package material Lead frame material Pin treatment Package weight g Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.46 TYP. 2/Dec. 11, 1996 DIP14-P-300-2.54 5 Package material Lead frame material Pin treatment Package weight (g)


    Original     		DIP8-P-300-2 DIP14-P-300-2 DIP16-P-300-2 DIP18-P-300-2 MIL-M-38510 MIL-STD-883 LGA 1156 PIN OUT diagram QSJ-44403 LGA 1150 Socket PIN diagram LGA 1155 Socket PIN diagram IC107-26035-20-G LGA 1151 PIN diagram REFLOW lga socket 1155 IC107-3204-G TB 2929 H alternative LGA 1155 pin diagram PDF

    ATMEL 234

    Abstract: ATMEL Packing Methods and Quantities ATMEL 210 atmel tape and reel ATMEL shipping label ATMEL Tape and Reel code ATMEL SOIC tape and reel ATMEL JEDEC SOIC atmel tape and reel JEDEC SOIC ATMEL Packing information JEDEC SOIC
    Text: Available Packing Methods and Quantities Atmel provides four different packing methods to provide maximum protection for our product and to best suit our customer's needs: 1 Shipping Tubes, 2) Shipping Trays, 3) Unit Packing, and 4) Tape and Reel. These first three


    Original     		0637B 10/98/xM ATMEL 234 ATMEL Packing Methods and Quantities ATMEL 210 atmel tape and reel ATMEL shipping label ATMEL Tape and Reel code ATMEL SOIC tape and reel ATMEL JEDEC SOIC atmel tape and reel JEDEC SOIC ATMEL Packing information JEDEC SOIC PDF

    DIP24-P-600-2

    Abstract: oki qfp tray SEPT24
    Text: Package Overview I Type Typical Sample Semiconductor Pin Counts Pitches [mm] OKI Suffix DIP Dual-in-line Package 8, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 42, 48 2.54 RA SDIP (Shrink Dual-in-line Package) 30, 42, 64 1.778 ZIP (Zig-Zag In-line Package) 20, 24, 28, 40


    Original     		100mil 70mil 50mil 40PQFP DIP24-P-600-2 oki qfp tray SEPT24 PDF