TTL SCHMITT-TRIGGER OPEN LOOP Search Results

TTL SCHMITT-TRIGGER OPEN LOOP Result Highlights (5)

Part	Manufacturer	Description
TCTH022BE	Toshiba Electronic Devices & Storage Corporation	Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Open-drain type / FLAG signal latch function
TCTH021BE	Toshiba Electronic Devices & Storage Corporation	Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Open-drain type
TCTH012BE	Toshiba Electronic Devices & Storage Corporation	Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=1μA / IDD=1.8μA / Open-drain type / FLAG signal latch function
TCTH011BE	Toshiba Electronic Devices & Storage Corporation	Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=1μA / IDD=1.8μA / Open-drain type
LBAA0QB1SJ-295	Murata Manufacturing Co Ltd	SX1262 MODULE WITH OPEN MCU

TTL SCHMITT-TRIGGER OPEN LOOP Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
PO61 Abstract: ATMEL 340 atmel 424 ATLS60 ATL60 ttl buffer 3.6v Tri-State Buffer bga ambit inverter circuit AOI222 ATMEL 218 Text: Features • • • • • • • • 0.6 µm Drawn Gate Length 0.5 µm Leff Sea-of-Gates Architecture with Triple Level Metal 5.0V, 3.3V and 2.0V Operation including Mixed Voltages On-chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and	Original	ATL60 0388C 11/99/xM PO61 ATMEL 340 atmel 424 ATLS60 ttl buffer 3.6v Tri-State Buffer bga ambit inverter circuit AOI222 ATMEL 218	PDF
3 to 8 bit decoder vhdl IEEE format Abstract: ATL60 ATLS60 PO61 ttl buffer Text: ATL60 Features x x x x x x x x 0.6Pm Drawn Gate Length 0.5Pm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and Manage Chip-to-Chip Clock Skew	Original	ATL60 ATL60 3 to 8 bit decoder vhdl IEEE format ATLS60 PO61 ttl buffer	PDF
TTL Schmitt-Trigger Inverters Abstract: Structure of D flip-flop DFFSR Tri-State Buffer CMOS TTL 3 input or gate ttl buffer TTL nand 3 input or gate 3 input Decoders actel PLL schematic AOI222 Text: ATL60 Features • • • • • • • • 0.6µm Drawn Gate Length 0.5µm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to	Original	ATL60 ATL60 TTL Schmitt-Trigger Inverters Structure of D flip-flop DFFSR Tri-State Buffer CMOS TTL 3 input or gate ttl buffer TTL nand 3 input or gate 3 input Decoders actel PLL schematic AOI222	PDF
Tri-State Buffer CMOS Abstract: PTS41 books schmitt trigger cmos buffer 8x buffer cmos ATL60 ATLS60 mux8n AOI222 Text: ATL60 Features • • • • • • • • 0.6µm Drawn Gate Length 0.5µm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to	Original	ATL60 ATL60 Tri-State Buffer CMOS PTS41 books schmitt trigger cmos buffer 8x buffer cmos ATLS60 mux8n AOI222	PDF
transistor nd8 Abstract: BT4R ISB28000 bt8c pMOS NAND GATE MUX21L AN720 BUT12 BUT18 BUT24 Text: ISB28000 SERIES HCMOS EMBEDDED ARRAY PRELIMINARY DATA FEATURES Combines Standard Cell features with Sea Of Gates time to market. 0.7 micron triple layer metal HCMOS process featuring self-aligned twin tub N and P wells, low resistance polysilicide gates and thin metal oxide.	Original	ISB28000 transistor nd8 BT4R bt8c pMOS NAND GATE MUX21L AN720 BUT12 BUT18 BUT24	PDF
Wideband FM Modulator schematic diagram using NE564 Abstract: SR01028 50MHz VCO schematic limiter circuit operation in basic fm demodulate SR01025 NE564N NE564 equivalent 80pf philips Trimmer capacitors vco 5MHz NE564D Text: Philips Semiconductors Product specification Phase-locked loop NE/SE564 DESCRIPTION PIN CONFIGURATIONS The NE/SE564 is a versatile, high guaranteed frequency phase-locked loop designed for operation up to 50MHz. As shown in the Block Diagram, the NE/SE564 consists of a VCO, limiter,	Original	NE/SE564 NE/SE564 50MHz. 50MHz R9-11 300pF NE564 SR01034 Wideband FM Modulator schematic diagram using NE564 SR01028 50MHz VCO schematic limiter circuit operation in basic fm demodulate SR01025 NE564N NE564 equivalent 80pf philips Trimmer capacitors vco 5MHz NE564D	PDF
UART TTL buffer Abstract: HCI Transport Layers STLC2410B STW5093 M16550 Text: STLC2410B BLUETOOTH BASEBAND PRELIMINARY DATA - REV. 1.1 1 • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES Bluetooth® V1.1 specification compliant Point-to-point, point-to-multi-point up to 7 slaves and scatternet capability Asynchronous Connection-Less (ACL) link	Original	STLC2410B 721kbps 32-bit 13MHz 64KByte 16-bit UART TTL buffer HCI Transport Layers STLC2410B STW5093 M16550	PDF
schmitt trigger 4093 Abstract: D16841 4017 decade counter 1-of-10 dual differential line driver 88c30 HC 4093 4013 astable 16-LINE TO 4-LINE PRIORITY ENCODERS 7 segment 40192 88c29 4011 astable Text: Revised April 1999 Functional Selection Table 1999 Fairchild Semiconductor Corporation MS500117.prf www.fairchildsemi.com Functional Selection Table February 1998 Gates Function CROSSVOLT Device Leads FACT FAST FASTr ALS AS LS S TTL ABT VCX LCX LVX LVT LVQ AC ACT	Original	MS500117 schmitt trigger 4093 D16841 4017 decade counter 1-of-10 dual differential line driver 88c30 HC 4093 4013 astable 16-LINE TO 4-LINE PRIORITY ENCODERS 7 segment 40192 88c29 4011 astable	PDF
Untitled Abstract: No abstract text available Text: STLC2410B BLUETOOTH BASEBAND PRELIMINARY DATA - REV. 1.1 1 • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES Bluetooth V1.1 specification compliant Point-to-point, point-to-multi-point up to 7 slaves and scatternet capability Asynchronous Connection-Less	Original	STLC2410B 32-bit 13MHz 64KByte 16-bit	PDF
NE564 Abstract: 50MHz VCO schematic Wideband FM Modulator schematic diagram using NE564 limiter circuit operation in basic fm demodulate 80pf philips Trimmer capacitors pll 564 schematic Wideband FM Modulator schematic diagram pll 564 50MHz VCO NE564N Text: Philips Semiconductors Product specification Phase-locked loop NE/SE564 DESCRIPTION PIN CONFIGURATIONS The NE/SE564 is a versatile, high guaranteed frequency phase-locked loop designed for operation up to 50MHz. As shown in the Block Diagram, the NE/SE564 consists of a VCO, limiter,	Original	NE/SE564 NE/SE564 50MHz. 50MHz NE564 300pF SR01034 NE564 50MHz VCO schematic Wideband FM Modulator schematic diagram using NE564 limiter circuit operation in basic fm demodulate 80pf philips Trimmer capacitors pll 564 schematic Wideband FM Modulator schematic diagram pll 564 50MHz VCO NE564N	PDF
74573 Abstract: 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432 7490 Decade Counter 74373 cmos dual s-r latch 2 bit magnitude comparator using 2 xor gates design a BCD counter using j-k flipflop Text: Semiconductor Logic Device Cross-Reference Here is a comprehensive cross-reference of TTL and CMOS chips that are readily available over the counter from such places as Maplin Electronics in the UK . Tables of both TTL and CMOS devices are provided along with tables grouping chips with the same functionality together.	Original		PDF
R240 Abstract: R242 R243 R245 R246 R251 Text: ST9 PERIPHERALS 1. INPUT / OUTPUT PORTS I/O PORTS Description l ST9+ can have up to 9 ports 8 bits each l Ports configuration is highly dependent on the device (cf I/O ports datasheet) l Each port is associated with a Data Register PxDR and is configured through 3 control registers PxC0, PxC1, PxC2	Original		PDF
AEC-Q100 Abstract: STLC2410B STW5093 HCI Transport Layers TFBGA132 Text: STLC2410B BLUETOOTH BASEBAND 1 • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES Bluetooth® V1.1 specification compliant Point-to-point, point-to-multi-point up to 7 slaves and scatternet capability Asynchronous Connection-Less (ACL) link	Original	STLC2410B 721kbps 32-bit 13MHz 64KByte 16-bit AEC-Q100 STLC2410B STW5093 HCI Transport Layers TFBGA132	PDF
cd4xxx Abstract: CD40107BKMSR CD4046BD 5962R9581301VXC 5962R9662501VEC 5962r9568101vcc 5962R9664401VXC 5962R9574401VXC 5962F9961801VXC 5962F9568902VXC Text: Radiation Hardened 13 DIGITAL/MILITARY/SPACE PRODUCT TREES ANALOG Selection Guides Radiation Hardened Amplifiers Selection Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Acquisition D/A Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	Original	5962F9954701VYA IS1-1825ASRH-8 5962F0251101QEC IS1-1825ASRH-Q 5962F0251101VEC IS1-2981RH-8 5962R0052001QVC IS1-2981RH-Q 5962R0052001VVC IS2-1009RH-8 cd4xxx CD40107BKMSR CD4046BD 5962R9581301VXC 5962R9662501VEC 5962r9568101vcc 5962R9664401VXC 5962R9574401VXC 5962F9961801VXC 5962F9568902VXC	PDF

M28R400CT Abstract: STLC2415 wireless remote control unit bluetooth h18 Text: STLC2415 BLUETOOTH BASEBAND WITH INTEGRATED FLASH PRELIMINARY DATA 1 • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES Figure 1. Package Bluetooth® V1.1 specification compliant SW compatible with STLC2410B-M28R400CT combination 2 layer class 4 PCB compatible	Original	STLC2415 STLC2410B-M28R400CT 32-bit M28R400CT STLC2415 wireless remote control unit bluetooth h18	PDF
PTS41 Abstract: CMOS GATE ARRAY buf8 Text: ATL60 Features • O.tHim Drawn Gate Length O.Stim Left Sea-of-Gates Architecture With Triple Level Metal • 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages • On Chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and Manage Chlp-to-Chip Clock Skew	OCR Scan	ATL60 ATL60 PTS41 CMOS GATE ARRAY buf8	PDF
Untitled Abstract: No abstract text available Text: M T C -1 2 0 0 0 C M O S 1 .2 u Standard Cell Library Services CMOS Family Features • Technology: - 1.2 micron tw in -w ell CMOS process w ith polycide gates, double layer m etal, linear Ihin oxide capacitors and high ohmic resistors - Shrink capability to	OCR Scan	BHDA08A BHAD12A BHSD14A	PDF
Untitled Abstract: No abstract text available Text: ATL60 Features • • • • • • • • 0.6\|.im D raw n G ate Length 0.5\|im Left S e a -o f-G a te s A rch ite c tu re W ith T rip le Level M etal 5.0 V o lt, 3.3 V o lt, and 2.0 V o lt O p e ra tio n In c lu d in g M ixed V o lta g e s On C h ip P h ase Locked Loop A v a ila b le to S y n th e s ize F req u en cies up to	OCR Scan	ATL60 ATL60	PDF
Untitled Abstract: No abstract text available Text: M T C - 2 2 0 0 0 C M O S 0 .7 n Standard Cell Family Services CMOS Family Features • Technology: CMOS 0 .7 m icron, double or triple la y e r m etal digital or m ix e d a n a lo g /d ig ita l processes, featu rin g self aligned tw in tub N an d P w ells, polycide or polysilicon	OCR Scan	I08CR 08SCR	PDF
14011b Abstract: hc7573 HC589 MC14XXX hc4078 HC4075 HC593 HC4017 TTL LOGIC HC590 Text: SURFACE MOUNT — MOS PRODUCTS continued Package 14 SOICN SOIC N SOICN SOICN SOICN Recluse Device Octal D-Type Flip-Flop, 3-State, Inverting Output Octal D-Type Flip-Flop, 3-State, Inv Output, TTL LL Octal Transparent Latch, 3-State Octal D-Type Transparent Latch, 3-State, TTL Logic Level	OCR Scan	HC564 HCT564 HC573 HCT573 HC574 HCT574 HC589 HC590 HC592 HC593 14011b hc7573 MC14XXX hc4078 HC4075 HC4017 TTL LOGIC	PDF
CA3237E Abstract: CA3237 an5020 Text: CA3237 £ 51 HARRIS U ü S E M I C O N D U C T O R IR Remote-Control Amplifier May 1992 Features Description • Integrated Circuit Package - 9-Pin SIP The CA3237* is a linear integrated circuit intended for infra red remote control receiver applications for TV receivers.	OCR Scan	CA3237 CA3237* 40kHz CA3237 1500m CA3237E an5020	PDF
CA3237E Abstract: ca3237 TA11167 IR sensor for 40khz IR remote control switch circuit diagram an5020 remotecontrol schematic diagram center tapped transformer 12v 3A TV IR remote control circuit diagram remote control receiver ir tv schematic Text: CA3237 fSl H A R IR IS S E M I C O N D U C T O R IR Remote-Control Amplifier May 1992 Features Description • Integrated Circuit Package - 9-Pin SIP The CA3237* is a linear integrated circuit intended lo r infra red remote control receiver applications for TV receivers.	OCR Scan	CA3237 CA3237* 40kHz -500HÂ CA3237E ca3237 TA11167 IR sensor for 40khz IR remote control switch circuit diagram an5020 remotecontrol schematic diagram center tapped transformer 12v 3A TV IR remote control circuit diagram remote control receiver ir tv schematic	PDF
nl 746 Abstract: nl 712 nl 836 fl1s2ax NL 714 B-01 FD1S3IX bit-slice FD1S3DX 2-bit binary full adder Text: A T & T MELEC I C 25E D Functional Index • QOSOOEb GOGMbflM 5 ■ 1.25\|i CMOS Library This section provides a quick overview of the functions available in AT&T’s 1 25n CMOS library. I/O Buffers u page BHidCod[D,H,7] TTL Bi-directional Buffer, Input with Hysteresis, Open Collector Output	OCR Scan	BIP02 nl 746 nl 712 nl 836 fl1s2ax NL 714 B-01 FD1S3IX bit-slice FD1S3DX 2-bit binary full adder	PDF
Wideband FM Modulator schematic diagram using NE564 Abstract: Philips FA 564 NE564 equivalent NE564 Text: Product specification Philips Semiconductors-Signetlcs Linear Products Phase-locked loop NE/SE564 PIN CONFIGURATIONS DESCRIPTION FEATURES The NE/SE564 is a versatile, high guaranteed frequency phase-locked loop designed for operation up to 50MHz. As shown in the Block Diagram, the NE/SE564	OCR Scan	NE/SE564 NE/SE564 50MHz. 50MHz 100nA. NE564 Wideband FM Modulator schematic diagram using NE564 Philips FA 564 NE564 equivalent	PDF

TTL SCHMITT-TRIGGER OPEN LOOP Search Results

TTL SCHMITT-TRIGGER OPEN LOOP Result Highlights (5)

TTL SCHMITT-TRIGGER OPEN LOOP Datasheets Context Search

PO61

3 to 8 bit decoder vhdl IEEE format

TTL Schmitt-Trigger Inverters

Tri-State Buffer CMOS

transistor nd8

Wideband FM Modulator schematic diagram using NE564

UART TTL buffer

schmitt trigger 4093

Untitled

NE564

74573

R240

AEC-Q100

cd4xxx

M28R400CT

PTS41

Untitled

Untitled

Untitled

14011b

CA3237E

CA3237E

nl 746

Wideband FM Modulator schematic diagram using NE564