ICS810001-21
Abstract: VCXO 74.25MHZ 1080P ITU-R601 74125 logic diagram X22 3A ics81000 SMPTE 1080p level a 74125 ic pin diagram
Text: DATA SHEET PRELIMINARY Integrated FEMTOCLOCKS DUAL VCXO Circuit VIDEO PLL Systems, Inc. ICS810001-21 ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL GENERAL DESCRIPTION FEATURES The ICS810001-21 is a member of the HiperClockS™ family of high performance clock
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ICS810001-21
ICS810001-21
199707558G
VCXO 74.25MHZ
1080P
ITU-R601
74125 logic diagram
X22 3A
ics81000
SMPTE 1080p level a
74125 ic pin diagram
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ICS810001-21
Abstract: ICS810001 810001BK-21 VCXO 27MHZ HSYNC 1080P ITU-R601 2222na
Text: PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS DUAL VCXO VIDEO PLL GENERAL DESCRIPTION FEATURES The ICS810001-21 is a member of the HiperClockS™ family of high performance clock HiPerClockS™ solutions from ICS. The ICS810001-21 is a PLL
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ICS810001-21
ICS810001-21
810001BK-21
ICS810001
810001BK-21
VCXO 27MHZ HSYNC
1080P
ITU-R601
2222na
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS DUAL VCXO VIDEO PLL GENERAL DESCRIPTION FEATURES The ICS810001-21 is a member of the HiperClockS™ family of high performance clock HiPerClockS™ solutions from ICS. The ICS810001-21 is a PLL
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ICS810001-21
ICS810001-21
810001BK-21
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VCXO 27MHZ HSYNC
Abstract: 810001DK-21LF
Text: PRELIMINARY ICS810001-21 FEMTOCLOCKS DUAL VCXO VIDEO PLL General Description Features The ICS810001-21 is a member of the HiperClockS™ family of high performance clock solutions from IDT. HiPerClockS™ The ICS810001-21 is a PLL based synchronous clock generator that is optimized for digital video
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ICS810001-21
560MHz
700MHz
3516484MHz,
973027MHz
12kHz
20MHz)
089ps
VCXO 27MHZ HSYNC
810001DK-21LF
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LM7711
Abstract: lmh1983 1080p30 to 625p DSA71604 720p25 720P59 9438 diode 1080i25 tcxo 27MHz VCXO 27MHZ HSYNC
Text: May 11, 2010 LMH1983 3G/HD/SD Video Clock Generator with Audio Clock General Description Features The LMH1983 is a highly-integrated programmable audio/ video A/V clock generator intended for broadcast and professional applications. It can replace multiple PLLs and VCXOs used in applications supporting SMPTE serial digital video
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LMH1983
LMH1983
LM7711
1080p30 to 625p
DSA71604
720p25
720P59
9438 diode
1080i25
tcxo 27MHz
VCXO 27MHZ HSYNC
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1080p30 to 625p
Abstract: LM7711 DSA71604 LMH1983 TCXO 14.85 27 mhz oscillator VCXO 27MHZ HSYNC
Text: LMH1983 3G/HD/SD Video Clock Generator with Audio Clock General Description Features The LMH1983 is a highly-integrated programmable audio/ video A/V clock generator intended for broadcast and professional applications. It can replace multiple PLLs and VCXOs used in applications supporting SMPTE serial digital video
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LMH1983
LMH1983
1080p30 to 625p
LM7711
DSA71604
TCXO 14.85
27 mhz oscillator
VCXO 27MHZ HSYNC
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TCXO 24.576MHz
Abstract: No abstract text available
Text: April 28, 2010 LMH1983 3G/HD/SD Video Clock Generator with Audio Clock General Description Features The LMH1983 is a highly-integrated programmable audio/ video A/V clock generator intended for broadcast and professional applications. It can replace multiple PLLs and VCXOs used in applications supporting SMPTE serial digital video
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LMH1983
TCXO 24.576MHz
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XV750CQ1
Abstract: XV750CQ1-01 SV-O3 QFP128 XV750C PAL-60 S4 5aa 4151II XV750 B1370
Text: Advanced Information XV750C NTSC/PAL/SECAM Digital Video Decoder Data Sheet Draft 1.03E Apr. 15, 2003 VDD-005-011-02 2003 IIX INC. XV750C Data Sheet Table of Contents 1. General Description. 1
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XV750C
VDD-005-011-02
XV750CQ1
XV750CQ1-01
SV-O3
QFP128
XV750C
PAL-60
S4 5aa
4151II
XV750
B1370
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PAP102
Abstract: LMH1983 PAC107 pic7801 PAC800 PAP101 PAC702 COC25 LP3878MR-ADJ pir320
Text: LMH1983 Evaluation Kit Users Guide LMH1983 Evaluation Kit Users Guide Version 1.0 2/4/10 Page 1 of 25 LMH1983 Evaluation Kit Users Guide INTRODUCTION The LMH1983 Evaluation Kit EVK allows for the evaluation of the LMH1983 3G/HD/SD Video Clock Generator with Audio Clock. The LMH1983 device is
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LMH1983
LMH1983
sofAX202
PAR4702
PAX203
PAP102
PAC107
pic7801
PAC800
PAP101
PAC702
COC25
LP3878MR-ADJ
pir320
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variable frequency drive block diagram
Abstract: FS6131-01
Text: FS6131-01 Programmable Line Lock Clock Generator IC 1.0 Features 3.0 ä Applications • Complete programmable control via I C -bus • Frequency Synthesis • Selectable CMOS or PECL compatible outputs • Line-Locked and Genlock Applications • External feedback loop capability allows genlocking
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FS6131-01
FS6131-01)
FS6131-01i)
FS6131-01
I840000
48MHz.
44MHz
52MHz
variable frequency drive block diagram
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FS6131-01
Abstract: No abstract text available
Text: 6 3URJUDPPDEOH /LQH /RFN &ORFN *HQHUDWRU ,& X T April 1999 1.0 Features 3.0 Applications • Complete programmable control via I C -bus • Frequency Synthesis • Selectable CMOS or PECL compatible outputs • Line-Locked and Genlock Applications
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FS6131-01)
FS6131-01i)
48MHz.
44MHz
52MHz
FS6131-01
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RC clock generator 12MHz
Abstract: CLOCK GENERATOR 100kHZ line lock pll Programmable Divider FS6131-01 NF800 nyquist plot xtal oscillator 300MHz cxm 4000 fs6031
Text: FS6131-01 Programmable Line Lock Clock Generator IC 1.0 Features 3.0 ä Applications • Complete programmable control via I C -bus • Frequency Synthesis • Selectable CMOS or PECL compatible outputs • Line-Locked and Genlock Applications • External feedback loop capability allows genlocking
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FS6131-01
FS6131-01)
FS6131-01i)
FS6131-01
48MHz.
44MHz
52MHz
ISO9001
RC clock generator 12MHz
CLOCK GENERATOR 100kHZ
line lock pll
Programmable Divider
NF800
nyquist plot
xtal oscillator 300MHz
cxm 4000
fs6031
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pap103
Abstract: PAP101 PIR203 pap102
Text: LMH1983 Evaluation Kit Users Guide LMH1983 Evaluation Kit Users Guide Version 1.0 2/4/10 Page 1 of 25 LMH1983 Evaluation Kit Users Guide INTRODUCTION The LMH1983 Evaluation Kit EVK allows for the evaluation of the LMH1983 3G/HD/SD Video Clock Generator with Audio Clock. The LMH1983 device is
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LMH1983
LMH1983
pap103
PAP101
PIR203
pap102
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FS6131-01
Abstract: FS6131-01G-XTD FS6131-01G-XTP fs6031
Text: FS6131 Programmable Line Lock Clock Generator IC 1.0 Key Features • • • • Complete programmable control via I2C -bus Selectable CMOS or PECL compatible outputs External feedback loop capability allows genlocking Tunable VCXO loop for jitter attenuation
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FS6131
FS6131-01
FS6131and
FS6131-01G-XTD
FS6131-01G-XTP
fs6031
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FS6131-01
Abstract: J-STD-020B
Text: FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet 1.0 Features • Complete programmable control via I2C -bus • Selectable CMOS or PECL compatible outputs • External feedback loop capability allows genlocking • Tunable VCXO loop for jitter attenuation
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FS6131-01/FS6131-01g
FS6131-01
J-STD-020B
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0054m
Abstract: fs6031
Text: FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet 1.0 Features • Complete programmable control via I2C -bus • Selectable CMOS or PECL compatible outputs • External feedback loop capability allows genlocking • Tunable VCXO loop for jitter attenuation
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FS6131-01/FS6131-01g
FS6131-01
FS6131-0equipment,
0054m
fs6031
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Untitled
Abstract: No abstract text available
Text: FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet 1.0 Features • • • • Complete programmable control via I2C -bus Selectable CMOS or PECL compatible outputs External feedback loop capability allows genlocking Tunable VCXO loop for jitter attenuation
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FS6131-01/FS6131-01g
FS6131-01
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MAPCA2000
Abstract: X32B DSA00152780 hitachi PLC equator VLIW architecture ac3 decoder toslink PAL to ITU-R BT.601/656 Decoder TV Tuner phillips 21 IEC958 free home theater circuit diagram for assemble
Text: Media Accelerated Processor for Consumer Appliances MAP-CA2000 Data Sheet DS#00006 2/5/2000 MAP-CA2000 Overview MAP-CA2000™ - Media Accelerated Processor for Consumer Appliances- offers a highly integrated single chip solution for multimedia products such as set-top boxes, digital TVs, video conferencing systems, medical imaging products, digital video
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MAP-CA2000TM
MAP-CA2000
MAP-CA2000
128-bit
MAPCA2000
X32B
DSA00152780
hitachi PLC
equator VLIW architecture
ac3 decoder toslink
PAL to ITU-R BT.601/656 Decoder
TV Tuner phillips 21
IEC958
free home theater circuit diagram for assemble
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Untitled
Abstract: No abstract text available
Text: Terasic THDB-SUM SDI HSMC Terasic SDI HSMC Board User Manual Document Version 1.00 Document Version 1.00 AUG 21, Aug. 20 2009 by Terasic Introduction Page Index INTRODUCTION. 1
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SECAM Encoders
Abstract: I2S* sony Dolby prologic II SP8890 SP8890C iso 13818-2 transport stream BT 151 PIN DIAGRAM PAL to ITU-R BT.601/656 Decoder LMD31 prologic II 5.1
Text: Datasheet SP8890C V02.01 Final 2000 SPaSE bv SP8890C Datasheet - Revision History Revision History Version 00.98 01.00 02.00 02.01 Date 27/02/1998 13/08/1998 07/09/1999 22/11/2000 Changes Pinning, data input, memory requirements, 2 Mbyte modes. Memory Requirements.
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SP8890C
NL009830303B01
SECAM Encoders
I2S* sony
Dolby prologic II
SP8890
SP8890C
iso 13818-2 transport stream
BT 151 PIN DIAGRAM
PAL to ITU-R BT.601/656 Decoder
LMD31
prologic II 5.1
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EBU-N10
Abstract: AK8850 CCIR601 CBPFS MH 7420
Text: ASAHI KASEI [AK8850] AK8850 NTSC Digital Video Decoder General Description The AK8850 decodes NTSC composite video, S-Video and Component Video signals 525/625 into digital formats. Digital output conforms to ITU-R BT.601 and ITU-R BT.656* YCrCb specifications. The AK8850 outputs
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AK8850]
AK8850
AK8850
AK8850.
10-Bit
EBU-N10
CCIR601
CBPFS
MH 7420
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EL4583
Abstract: EL4584 EL4585 EL4585CN EL4585CS EL4585CS-T13 EL4585CS-T7 EL4585CSZ EL4585CSZ-T7
Text: EL4585 Data Sheet July 1, 2005 Horizontal Genlock, 8FSC Features The EL4585 is a PLL Phase Lock Loop sub-system, designed for video applications and also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS-compatible pixel clock (CLK OUT)
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EL4585
EL4585
36MHz.
FN7175
36MHz,
EL4583
EL4584
EL4585CN
EL4585CS
EL4585CS-T13
EL4585CS-T7
EL4585CSZ
EL4585CSZ-T7
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fdk vco
Abstract: vco fdk 936KB "initial synchronization"
Text: AMI FS6131-01 AMERICAN MICROSYSTEMS, INC. Line-Locked Clock Generator IC Preliminary Information July 1998 1.0 Features 3.0 Applications • Complete programmable control via l2C'“-bus • Frequency Synthesis • Selectable CMOS or PECL compatible outputs
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FS6131-01
FS6131-01
48MHz.
44MHz
52MHz
IS08001
fdk vco
vco fdk
936KB
"initial synchronization"
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IS88001
Abstract: NF-20 schematic diagram vga to av 36ann it30
Text: •Aim AMERICAN MICROSYSTEMS, INC, FS6131-01 Programmable Line Lock Clock Generator IC April 1999 1.0 Features 3.0 Applications • Complete programmable control via l2C “-bus • Frequency Synthesis • Selectable CMOS or PECL compatible outputs • External feedback loop capability allows genlocking
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FS6131-01
FS6131
FS6131-01
cl1840000
48MHz.
44MHz
52MHz
IS08001
IS88001
NF-20
schematic diagram vga to av
36ann
it30
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