74HCTLS
Abstract: el 519
Text: Zyfi vx ZXS4HCTLS Ë U ZX74HCTLS Ê February 1985 T r ip le 3 -In p u t N A N D E G a te ^ OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain three independent 3-input NAND
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ZX74HCTLS
54/74LS
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el 519
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74HCTLS
Abstract: No abstract text available
Text: Zvtrex ZX54HCTLS ZX74HCTLS February 1985 78A Dual J-K Flip-Flops with Preset, Common Clear & Common Clock O B J E C T IV E SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These parts consist of two oegatjye-edge-triggered J-K
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ZX54HCTLS
ZX74HCTLS
54/74LS
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74HCTLS
Abstract: No abstract text available
Text: Z y tr e x ZX54HCTLS M ZX74HCTLS M February 1985 M Hex Schmitt-Trigger Inverters OBJECTIVE SPECIFICATIONS Features Description • Function, pln-out, speed and drive compatibility with 54/74LS logic family These Schm itt-trigger devices contain six independent
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ZX54HCTLS
ZX74HCTLS
54/74LS
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74hctls
Abstract: No abstract text available
Text: Zytrex ZX54HCTLS ZX74HCTLS no f M^ Quad 2-Input NOR Gates February 1905 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These d e vice s con tain fo u r in d e p e n d e n t 2 -in put N O R
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54/74LS
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74hctls
Abstract: No abstract text available
Text: Zytrex ZX54HCTLS ZX74HCTLS 73A Dual J-K Negative-Edge-Triggered Flip-Flops with Clear Februa ry 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain two independent J-K negativeedge-triggered flip-flops. A low level at the CLR input
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ZX54HCTLS
ZX74HCTLS
54/74LS
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74hctls
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74HCTLS
Abstract: No abstract text available
Text: Zytrex ZX54HCTLS ZX74HCTLS February 1985 273 Octal D-Type Flip-Flops with Clear OBJECTIVE SPECIFICATIONS Features Description • Eight positive-edge-triggered D-type flipflops with single-rail outputs these devices are high-speed octal registers. They con
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ZX54HCTLS
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54/74LS
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74LS TTL 245
Abstract: 74HCTLS 74hctl PPT Diode specifications
Text: Zytrex ZX54HCTLS ZX74HCTLS February 1985 245 Octal Bus Transceivers with 3-State Outputs OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These high-speed octal bus transceivers are designed
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ZX54HCTLS
ZX74HCTLS
54/74LS
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74LS TTL 245
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74hctl
PPT Diode specifications
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74HCTLS
Abstract: No abstract text available
Text: Zvtrex ZX54HCTLS ZX74HCTLS 138 3-Line to 8-Line Decoders/Multiplexers February 1985 OBJECTIVE SPECIFICATIONS Features Description m Designed specifically for high-speed memory These devices are designed to be used in high-perform ance m em ory-decoding or data-routing applications re
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ZX54HCTLS
ZX74HCTLS
54/74LS
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74HCTLS
Abstract: diode S4 596
Text: Zytrex ZX54HCTLS ZX74HCTLS February 1985 191 Synchronous 4-Bit Up/Down Binary Counters OBJECTIVE SPECIFICATIONS Features tion e lim in ates the o u tp u t co u n tin g s p ike s no rm a lly a s s o ciate d w ith a syn ch ro n o u s rip ple clo ck cou nters.
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ZX74HCTLS
S4/74LS
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diode S4 596
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74HCTLS
Abstract: and cmos Zytrex
Text: Zvtrex ZX54HCTLS Æ ZX74HCTLS F e b ru a ry 1985 i S m^ Dual Retriggerable Monostable Multivibrator OBJECTIVE SPECIFICATIONS Features Description • Simple pulse width formula T = RC The '423 contains two retriggerable monostable multivi brators that feature both a negative, A, and a positive, B,
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ZX54HCTLS
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54/74LS
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and cmos
Zytrex
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HCTLS
Abstract: 74hctls
Text: Z v t n ZX54HCTLS M ZX74HCTLS x February 1985 Quad 2-Input AND Gates with Open-Drain Outputs OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-Input AND
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ZX54HCTLS
ZX74HCTLS
54/74LS
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HCTLS
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74hctls
Abstract: No abstract text available
Text: Zvtrex ZXS4HCTLS ZX74HCTLS 257 %æ&258 Quad 2-Line to 1-Line Data Selector/ Multiplexers with 3-State Outputs February 1985 OBJECTIVE SPECIFICATIONS Description Features The '257 and ’258 multiplex signals from four-bit data sources to four-output data lines in bus organized sys
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ZX74HCTLS
ss258
S4/74LS
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sys16
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74HCTLS
Abstract: hctls574 HCTLS
Text: Zytrex ZX54HCTLS ZX74HCTLS February 1985 574 Octal D-Type Flip-Flops with 3-State Outputs OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family ■ Low power consumption characteristic of
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ZX74HCTLS
54/74LS
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hctls574
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K413
Abstract: 74HCTLS Zytrex 161
Text: # MJ Lmm ZXS4HCTLS § ZX74HCTLS M Februa,y1985 t ZX54HCTLS ZX74HCTLS M Ë m a Ê WÂ À t m Synchronous 4-Bit Binary Counters O B JE C T IV E S P E C IF IC A T IO N S ' * Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family
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ZX54HCTLS
ZX74HCTLS
54/74LS
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K413
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Zytrex 161
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74HCTLS
Abstract: No abstract text available
Text: Z v tre x ZX54HCTLS § ZX74HCTLS M 8-Bit Parallel-ln/Serial-Out Shift Registers with Clear February 1985 OBJECTIVE SPECIFICATIONS Features Description • Synchronous load These devices feature parallel-in or serial-in, serial-out registers, gated clock inputs and an overriding clear in
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ZX54HCTLS
ZX74HCTLS
54/74LS
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74hctls
Abstract: Zytrex OR gate
Text: Z v t r e ZXS4HCTLS ZX74HCTLS x _ K A Quad 2-Input OR Gates February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, ptn-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input OR gates. They perform the Boolean functions Y = A + B
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54/74LS
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74hctls
Zytrex OR gate
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74HCTLS
Abstract: diode sy 171 sy 171 74hctl
Text: Z v tr e ZXS4HCTLS ZX74HCTLS x 6 4 z x k h c t ls 6 4 3 Octal Bus Transceivers February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These high-speed octal bus transceivers are designed
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ZX74HCTLS
54/74LS
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diode sy 171
sy 171
74hctl
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74HCTLS
Abstract: No abstract text available
Text: Zytrex ZXS4HCTLS ZX74HCTLS Februa ry 1985 74A Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain two independent positive-edgetriggered D-type flip-flops. Each flip-flop has its own
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ZX54HCTLS
ZX74HCTLS
54/74LS
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74HCTLS
Abstract: No abstract text available
Text: Z v t r e ZXS4HCTLS M M g ZX74HCTLS § x Quad 2-Input NAND Gates with Opert-Drain Outputs February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input NAND
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74HCTLS
Abstract: 1411D
Text: Zyfrex ZX54HCTLS # # ZX74HCTLS M M February 1985 •» 4-Bit D-Type Registers with 3-State Outputs OBJECTIVE SPECIFICATIONS Features Description ■ Gated output control lines for enabling or disabling the outputs These 4-bit registers contain D-type flip-flops with 3-state
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
-556C
74HCTLS
1411D
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74HCTLS
Abstract: No abstract text available
Text: h ftr e ZX54HCTLS ZX74HCTLS x § # ZX54HCTLS ZX74HCTLS Dual AND-OR-Invert Gates and Dual AND-OR Gates February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family The '51 performs the following Boolean functions:
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74hctls
Abstract: si158
Text: h flwar ZX54HCTLS ZX74HCTLS February 1985 157 zxm h c tls 158 Quad 2-Line to 1-Line Data Selector/Multiplexers OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These are data selector/multiplexers which select a 4-bit
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ZX54HCTLS
ZX74HCTLS
54/74LS
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hctlsi57,
hctlsi58
74HCTLS
54HCTLS
Ta--55Â
si158
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74HCTLS
Abstract: HCTLS
Text: Z v t r e ZXS4HCTLS # ZX74HCTLS M x February 1985 t M J MM # #• Dual J-K Negative-Edge-Triggered Flip-Flops with Clear OBJECTIVE SPECIFICATIONS Features Description ■ Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain two independent J-K negativeedge-triggered flip-flops. A low level at the CLR input
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ZX74HCTLS
54/74LS
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HCTLS
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74HCTLS
Abstract: No abstract text available
Text: Zvtrex 540 SSS&541 ZX54HCTLS ZX74HCTLS Octal Buffers and Line Drivers with 3-State Outputs F ebrua ry 1985 OBJECTIVE SPECIFICATIONS Features Description m Function, pin-out, speed and drive The '540 and ’541 are general purpose high-speed octal line drivers/buffers with 3-state outputs. The inputs and
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ZX54HCTLS
ZX74HCTLS
S4/74LS
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