74LVC1G57
Abstract: 74LVC1G57GF 74LVC1G57GM 74LVC1G57GV 74LVC1G57GW
Text: 74LVC1G57 Low-power configurable multiple function gate Rev. 4 — 15 October 2010 Product data sheet 1. General description The 74LVC1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
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74AUP1G57
Abstract: 74AUP1G57GF 74AUP1G57GM 74AUP1G57GW JESD22-A114-C transistor VT 209 M CDM 12.6 Philips
Text: 74AUP1G57 Low-power configurable multiple function gate Rev. 01. — 16 January 2006 Preliminary data sheet 1. General description The 74AUP1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
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transistor VT 209 M
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Abstract: No abstract text available
Text: 74LVC1G57 Low-power configurable multiple function gate Rev. 5 — 22 September 2011 Product data sheet 1. General description The 74LVC1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
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Text: 74AUP1G57 Low-power configurable multiple function gate Rev. 5 — 25 November 2011 Product data sheet 1. General description The 74AUP1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
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74AUP1G57
Abstract: 74AUP1G57GF 74AUP1G57GM 74AUP1G57GW
Text: 74AUP1G57 Low-power configurable multiple function gate Rev. 4 — 20 July 2010 Product data sheet 1. General description The 74AUP1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
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Text: 74AXP1G57 Low-power configurable multiple function gate Rev. 1 — 25 June 2013 Preliminary data sheet 1. General description The 74AXP1G57 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR,
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74AUP1T57
Abstract: 74AUP1T57GF 74AUP1T57GM 74AUP1T57GW JESD22-A114E
Text: 74AUP1T57 Low-power configurable gate with voltage-level translator Rev. 02 — 3 August 2009 Product data sheet 1. General description The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic
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001aab588
Abstract: No abstract text available
Text: 74LVC1G57 Low-power configurable multiple function gate Rev. 02 — 11 September 2006 Product data sheet 1. General description The 74LVC1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
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74AUP1T57
Abstract: 74AUP1T57GF 74AUP1T57GM 74AUP1T57GW
Text: 74AUP1T57 Low-power configurable gate with voltage-level translator Rev. 3 — 21 July 2010 Product data sheet 1. General description The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic
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74LVC1G57
Abstract: 74LVC1G57GF 74LVC1G57GM 74LVC1G57GV 74LVC1G57GW JESD22-A114E
Text: 74LVC1G57 Low-power configurable multiple function gate Rev. 03 — 19 July 2007 Product data sheet 1. General description The 74LVC1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
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Text: 74AUP1T57 Low-power configurable gate with voltage-level translator Rev. 5 — 15 August 2012 Product data sheet 1. General description The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic
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74AUP1G57
Abstract: 74AUP1G57GF 74AUP1G57GM 74AUP1G57GW JESD22-A114E
Text: 74AUP1G57 Low-power configurable multiple function gate Rev. 03 — 22 June 2009 Product data sheet 1. General description The 74AUP1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
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Untitled
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Text: 74LVC1G57 Low-power configurable multiple function gate Rev. 6 — 6 December 2011 Product data sheet 1. General description The 74LVC1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
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74AUP1T57
Abstract: 74AUP1T57GF 74AUP1T57GM 74AUP1T57GW JESD22-A114E
Text: 74AUP1T57 Low-power configurable gate with voltage-level translator Rev. 01 — 3 January 2008 Product data sheet 1. General description The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic
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Text: 74LVC1G57 Low-power configurable multiple function gate Rev. 6 — 6 December 2011 Product data sheet 1. General description The 74LVC1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
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74AUP1G57
Abstract: 74AUP1G57GF 74AUP1G57GM 74AUP1G57GW JESD22-A114D
Text: 74AUP1G57 Low-power configurable multiple function gate Rev. 01 — 23 November 2006 Product data sheet 1. General description The 74AUP1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
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ttl NAND gate circuit
Abstract: 74LVC1G57 74LVC1G57GM 74LVC1G57GV 74LVC1G57GW
Text: 74LVC1G57 Low-power configurable multiple function gate Rev. 01 — 6 September 2004 Product data sheet 1. General description The 74LVC1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
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74LVC1G57-Q100
Abstract: No abstract text available
Text: 74LVC1G57-Q100 Low-power configurable multiple function gate Rev. 1 — 15 April 2014 Product data sheet 1. General description The 74LVC1G57-Q100 provides configurable multiple functions. Eight patterns of 3-bit input, determine the output state. The user can choose the logic functions AND, OR,
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NXP PN65n
Abstract: NXP PN544 PN544 hardware design guide NXP PN544 Antenna Design Guide nfc PN65N PN544 PN544 NFC controller nxp pn544 antenna design PN544 NFC PN544 nxp
Text: Application guide Portable devices and mobile handsets Enhancing the user experience, simplifying the design Introduction Your partner for portable devices and mobile handsets NXP Semiconductors is a recognized leader in portable and mobile applications. We offer a comprehensive portfolio of best-in-class solutions
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74AUP1G57
Abstract: 74AUP1G57GF 74AUP1G57GM 74AUP1G57GW JESD22-A114E
Text: 74AUP1G57 Low-power configurable multiple function gate Rev. 02 — 23 March 2009 Product data sheet 1. General description The 74AUP1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
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Untitled
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Text: 74AUP1T57 Low-power configurable gate with voltage-level translator Rev. 4 — 1 December 2011 Product data sheet 1. General description The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic
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Text: 74AUP1G57 Low-power configurable multiple function gate Rev. 6 — 15 August 2012 Product data sheet 1. General description The 74AUP1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
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