PC MOTHERBOARD CIRCUIT diagram for i3
Abstract: empire state of mine FM3565 FM3565M20 FM3565M20X FM3565MT20 FM3565MT20X MT20 MTC20 i5 MOTHERBOARD CIRCUIT diagram only
Text: FM3565 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID General Description The serial port is an IIC compatible slave-only interface and supports both 100kbit and 400kbit modes of operation. The port is used to read the I-Port and to write data to the internal nonvolatile registers. The FM3565 is fabricated with advanced CMOS
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FM3565
100kbit
400kbit
FM3565
PC MOTHERBOARD CIRCUIT diagram for i3
empire state of mine
FM3565M20
FM3565M20X
FM3565MT20
FM3565MT20X
MT20
MTC20
i5 MOTHERBOARD CIRCUIT diagram only
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RS423A
Abstract: L6180 L6180A L6180D L6181 RS232A RS232D RS422A PLCC28 package
Text: L6180 L6181 OCTAL LINE RECEIVER ADVANCE DATA OCTAL LINE RECEIVER FOR: - EIA STD RS232D RS423A RS422A - CCIT V.10 V.11 V.28 X.26 NO EXTERNAL COMPONENTS INPUT FAIL SAFING CAPABILITY HIGH CROSSTALK REJECTION L6180 DATA RATE < 100KBIT/S L6181 DATA RATE < 1MBIT/S
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L6180
L6181
RS232D
RS423A
RS422A
L6180
100KBIT/S
L6181
L6180/1
RS232A
RS423A
L6180A
L6180D
RS232D
RS422A
PLCC28 package
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FM3570MT20
Abstract: 3570 mt20 FM3570 FM3570M20 FM3570M20X FM3570MT20X MT20 MTC20
Text: FM3570 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID General Description The serial port is an IIC compatible slave-only interface and supports both 100kbit and 400kbit modes of operation. The port is used to read the I-Port, write data to the internal non-volatile
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FM3570
100kbit
400kbit
FM3570
FM3570MT20
3570 mt20
FM3570M20
FM3570M20X
FM3570MT20X
MT20
MTC20
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Untitled
Abstract: No abstract text available
Text: Optical Sensor LTR-507ALS-01 Description The LTR-507ALS-01 is an integrated I2C digital light Features • sensor [ALS] and proximity sensor [PS] with built-in LED I2C interface Standard mode@100kbit/s, Fast Mode@400kbit/s and High Speed [email protected]/s driver, in a miniature chipled lead-free surface mount
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LTR-507ALS-01
LTR-507ALS-01
100kbit/s,
400kbit/s
127mm
BNS-OD-FC002/A4
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Untitled
Abstract: No abstract text available
Text: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590 – DECEMBER 1997 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps Pulse Skew, tsk(p), Less Than 500 ps
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CDC319
10-LINE
SCAS590
1-to-10
MIL-STD-883,
28-Pin
scas590
CDC319DBR
CDC319IBIS
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FTL3-2
Abstract: 8 bit modified booth multipliers S3C3410X 0xc01c IRM bed
Text: 22-S3-C3410X-062001 USER'S MANUAL S3C3410X 16-Bit CMOS Microcontrollers Revision 2 NOTIFICATION OF REVISIONS ORIGINATOR: Samsung Electronics, SOC Development Group, Ki-Heung, South Korea PRODUCT NAME: S3C3410X RISC Microcontroller DOCUMENT NAME: S3C3410X User's Manual, Revision 2
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22-S3-C3410X-062001
S3C3410X
16-Bit
S3C3410X
22-S3-C3410X-06-2001
FTL3-2
8 bit modified booth multipliers
0xc01c
IRM bed
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Untitled
Abstract: No abstract text available
Text: CDCE913 CDCEL913 www.ti.com SCAS849B – JUNE 2007 – REVISED DECEMBER 2007 Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs • FEATURES 1 • Member of Programmable Clock Generator Family – CDCE913/CDCEL913: 1-PLL, 3 Outputs
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CDCE913
CDCEL913
SCAS849B
CDCE913/CDCEL913:
CDCE925/CDCEL925:
CDCE937/CDCEL937:
CDCE949/CDCEL949:
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Graphic equalizer circuit diagram
Abstract: TDA7318 TDA7316 i2c graphic equalizer equalizer diagram and function tda731x
Text: TDA7316 FOUR BANDS DIGITAL CONTROLLED GRAPHIC EQUALIZER VOLUME CONTROL IN 0.375dB STEP FOUR BANDS STEREO GRAPHIC EQUALIZER CENTER FREQUENCY, BANDWIDTH, MAX BOOST/CUT DEFINED BY EXTERNAL COMPONENTS ±14dB CUT/BOOST CONTROL IN 2dB/STEP ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS
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TDA7316
375dB
TDA7316
625dB
Graphic equalizer circuit diagram
TDA7318
i2c graphic equalizer
equalizer diagram and function
tda731x
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Untitled
Abstract: No abstract text available
Text: MC9S12XDP512 Data Sheet HCS12X Microcontrollers MC9S12XDP512 Rev. 2.10 5/2005 freescale.com MC9S12XDP512 Data Sheet covers MC9S12XDT384 & MC9S12XA512 MC9S12XDP512V2 Rev. 2.10 5/2005 To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
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MC9S12XDP512
HCS12X
MC9S12XDP512
MC9S12XDT384
MC9S12XA512
MC9S12XDP512V2
MC9S12XDP512V1
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Untitled
Abstract: No abstract text available
Text: MC9S12XDP512 Data Sheet HCS12X Microcontrollers MC9S12XDP512 Rev. 2.09 5/2005 freescale.com MC9S12XDP512 Data Sheet covers MC9S12XDT384 & MC9S12XA512 MC9S12XDP512V2 Rev. 2.09 5/2005 To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
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MC9S12XDP512
HCS12X
MC9S12XDP512
MC9S12XDT384
MC9S12XA512
MC9S12XDP512V2
MC9S12XDP512V1
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Untitled
Abstract: No abstract text available
Text: MC9S12ZVHY-Family Reference Manual HCS12 Microcontrollers MC9S12ZVHYRMV1 Rev. 1.00 09/2013 freescale.com To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
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MC9S12ZVHY-Family
HCS12
MC9S12ZVHYRMV1
S12ZCPU
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CDC318
Abstract: No abstract text available
Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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CDC318
18-LINE
SCAS587B
1-to-18
MIL-STD-883,
48-Pin
CDC318
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em78p372
Abstract: EM78P374NSO24J
Text: EM78P374N 8-Bit Microcontroller Product Specification DOC. VERSION 1.4 ELAN MICROELECTRONICS CORP. January 2014 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo
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EM78P374N
em78p372
EM78P374NSO24J
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generator cr 665 bosch
Abstract: BOSCH 0 281 002 709 MC9S12ZVM
Text: MC9S12ZVM-Family Reference Manual HCS12 Microcontrollers Rev. 1.3 20 JAN 2014 MC9S12ZVMRMV1 freescale.com To provide the most up-to-date information, the document revision on the Internet is the most current. A printed copy may be an earlier revision. To verify you have the latest information available, refer to :
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MC9S12ZVM-Family
HCS12
MC9S12ZVMRMV1
S12ZCPU
generator cr 665 bosch
BOSCH 0 281 002 709
MC9S12ZVM
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ps3 power supply wires
Abstract: 106 M1 DIP20 SO20 TDA7346 TDA7346D kc01 PS3 transmitter
Text: TDA7346 DIGITAL CONTROLLED SURROUND SOUND MATRIX 1 STEREO INPUT THREE INDEPENDENT SURROUND MODES ARE AVAILABLE MOVIE, MUSIC AND SIMULATED - MUSIC: 4 SELECTABLE RESPONSES - MOVIE AND SIMULATED: 256 SELECTABLE RESPONSES TWO INDEPENDENT INPUT ATTENUATORS IN 0.31dB FOR BALANCE FACILITY
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TDA7346
DIP20
DIP20)
TDA7346D
TDA7346
680nF
100nF
ps3 power supply wires
106 M1
DIP20
SO20
TDA7346D
kc01
PS3 transmitter
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MC9S12XHZ512
Abstract: S12X9SECV2 FTX512K4 hcs12 moda modb xgate LFSR freescale MC9S12XHZ256 MSCAN stepper motor id27 freescale superflash MC9S12XHZ384
Text: MC9S12XHZ512 Data Sheet Covers MC9S12XHZ384, MC9S12XHZ256 HCS12X Microcontrollers MC9S12XHZ512V1 Rev. 1.03 1/2007 freescale.com MC9S12XHZ512 Data Sheet MC9S12XHZ512V1 Rev. 1.03 1/2007 To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
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MC9S12XHZ512
MC9S12XHZ384,
MC9S12XHZ256
HCS12X
MC9S12XHZ512V1
MC9S12XHZ512
S12X9SECV2
FTX512K4
hcs12 moda modb xgate
LFSR freescale
MC9S12XHZ256
MSCAN
stepper motor id27
freescale superflash
MC9S12XHZ384
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USB2524
Abstract: 56-PIN QFN-56 USB2524-ABZJ 4 port usb2.0 hub
Text: USB2524 USB MultiSwitchTM Hub PRODUCT FEATURES Datasheet USB2.0 Compatible 4-Port Hub with two upstream host port connections — Provides electronic reconfiguration and re-assignment of any of its 4 downstream ports to either of two upstream host ports “on-the-fly” .
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USB2524
USB2524
56-Pin
QFN-56
USB2524-ABZJ
4 port usb2.0 hub
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LTC2489
Abstract: sot-23 marking code 2fn
Text: LTC2489 16-Bit 2-/4-Channel ΔΣ ADC with Easy Drive Input Current Cancellation and I2C Interface FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION Up to 2 Differential or 4 Single-Ended Inputs Easy DriveTM Technology Enables Rail-to-Rail
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LTC2489
16-Bit
600nV
02LSB
50Hz/60Hz
15ppm
LTC2493/LTC2489
LTC2493
24-Bit
LTC2487/LTC2489
LTC2489
sot-23 marking code 2fn
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LEA6S0001
Abstract: No abstract text available
Text: locate, communicate, accelerate LEA-6 u-blox 6 GPS Modules Data Sheet Abstract Technical data sheet describing the cost effective, high-performance u-blox 6 based LEA-6 series of GPS modules, that bring the high performance of the u-blox 6 position engine to the industry
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G6-HW-09004-E2
LEA6S0001
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Untitled
Abstract: No abstract text available
Text: Low Power PCM Repeaters ANALOG DEVICES □ RPT-86/RPT-87 FEATURES • • • • • w ithT I 1,544Mbit/s , CEPT/E1 (2.048Mbit/s), and T1C (3.152Mbit/s) systems. Low Power Consumption (56mW) Single-Supply Operation Wide Data Rate Range <100kbit/s to >3Mbit/s
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RPT-86/RPT-87
544Mbit/s)
048Mbit/s)
152Mbit/s)
100kbit/s
RPT-87)
RPT-86/RPT-87
RPT-86
RPT-87
RPT-86/87
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state diagram for air conditioner
Abstract: L6180 L6180A L6180D L6181 RS232A RS232D RS422A RS423A
Text: SGS-THOMSON L6180 L6181 OCTAL LINE RECEIVER PRODUCT PREVIEW • OCTAL LINE RECEIVER FOR: - EIA STD RS232D RS423A RS422A - CCIT V.10 V.11 V.28 X.26 ■ NO EXTERNAL COMPONENTS ■ INPUT FAIL SAFING CAPABILITY ■ HIGH CROSSTALK REJECTION ■ L6180 DATA RATE < 100KBIT/S
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L6180
L6181
RS232D
RS423A
RS422A
100KBIT/S
L6181
L6180/1
RS232A
state diagram for air conditioner
L6180A
L6180D
RS232D
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Digital Oscilloscope Preamplifier
Abstract: 86187 RPT86FP RPT86FQ RPT87FP RPT87FQ
Text: ANALO G D EVICES Low Power PCM Repeaters RPT-86/RPT-87 w ith T I 1.544Mbit/s , CEPT/E1 (2.048Mbit/s), and T1C (3.152Mbit/s) systems. FEATURES • • • • • Low Power Consum ption (56mW) Single-Supply Operation W ide Data Rate Range <100kbit/s to >3M bit/s
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RPT-86/RPT-87
100kbit/s
RPT-87)
RPT86FQ
RPT86FP
RPT86FStt
RPT87FQ
RPT87FP
RPT87FSn
RPT-86
Digital Oscilloscope Preamplifier
86187
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Untitled
Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICS9148-60 Pentium/Pro System Clock Chip General Description The IC S9148-60 is part o f a reduced pin count two-chip clock solution for designs using an Intel BX style chipset. Companion SDRAM buffers are ICS9179-11 an d -12.
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ICS9148-60
S9148-60
ICS9179-11
8-10dB.
100MHz
ICS9248F-60
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NE6753
Abstract: audiom PHILIP A7 A7B0 D053 NE5753 NE5753D NE5753DK SA5752 SA5753
Text: PHILIPS INTERNATIONAL bOE » • ?110fi2b 0053^03 T3T « P H I N Objective pacification Philip« Sem iconductor* RF Communication* Product* NE/SA5753 Audio processor-filter and control section DESCRIPTION FEATURES The NE/SA5753 is a high performance low power CMOS audio signal processing system
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7110fl5b
110fi2b
NE/SA5753
NE/SA5753
300-3000Hz)
NE6753
audiom
PHILIP A7
A7B0
D053
NE5753
NE5753D
NE5753DK
SA5752
SA5753
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