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    54LS109 Search Results

    54LS109 Result Highlights (3)

    Part ECAD Model Manufacturer Description Download Buy
    SNJ54LS109AJ Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Preset And Clear 16-CDIP -55 to 125 Visit Texas Instruments Buy
    SNJ54LS109AW Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Preset And Clear 16-CFP -55 to 125 Visit Texas Instruments Buy
    SN54LS109AJ Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Preset And Clear 16-CDIP -55 to 125 Visit Texas Instruments
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    54LS109 Price and Stock

    Rochester Electronics LLC SN54LS109AJ

    54LS109A DUAL J-K POSITIVE-EDGE-
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    DigiKey SN54LS109AJ Bulk 30
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    Rochester Electronics LLC SNJ54LS109AJ

    54LS109A DUAL J-K POSITIVE-EDGE-
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    DigiKey SNJ54LS109AJ Bulk 30
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    Teledyne e2v DM54LS109J/883

    DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLO - Rail/Tube (Alt: DM54LS109J/883)
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    Teledyne e2v DM54LS109J/883 14 Weeks
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    Teledyne e2v JD54LS109BEA

    FLIP-FLOP, JK, DUAL - Rail/Tube (Alt: JD54LS109BEA)
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    Avnet Americas JD54LS109BEA Tube 250
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    Teledyne e2v JD54LS109B2C

    FLIP-FLOP, JK, DUAL - Rail/Tube (Alt: JD54LS109B2C)
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    Avnet Americas JD54LS109B2C Tube 250
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    Find more 54LS109 price and stock on Findchips.com

    54LS109 Datasheets (20)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    54LS109 National Semiconductor Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs Original PDF
    54LS109 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    54LS109 Raytheon Dual J-K Posilive-Edge-Triggered Flip-Flop Scan PDF
    54LS109A/BEAJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS109A/BFAJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS109AM/B2AJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS109DM Fairchild Semiconductor Dual JK Positive Edge Triggered Flip-Flop Scan PDF
    54LS109DM Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS109DMQB National Semiconductor Dual Positive-Edge-Triggered J-Inverted K Flip-Flop with Preset, Clear, and Complementary Outputs Original PDF
    54LS109DMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS109DMQB National Semiconductor 7 V, dual positive-edge-triggered master-slave J-K flip-flop with preset, clear and complementary output Scan PDF
    54LS109DMQB National Semiconductor Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs Scan PDF
    54LS109FM Fairchild Semiconductor Dual JK Positive Edge Triggered Flip-Flop Scan PDF
    54LS109FMQB National Semiconductor Dual Positive-Edge-Triggered J-Inverted K Flip-Flops with Preset, Clear, and Complementary Outputs Original PDF
    54LS109FMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS109FMQB National Semiconductor 7 V, dual positive-edge-triggered master-slave J-K flip-flop with preset, clear and complementary output Scan PDF
    54LS109FMQB National Semiconductor Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs Scan PDF
    54LS109J National Semiconductor Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs Original PDF
    54LS109M National Semiconductor Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs Original PDF
    54LS109N National Semiconductor Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs Original PDF

    54LS109 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: 54LS109,54LS109A,DM74LS109A 54LS109 54LS109A DM74LS109A Dual Positive-Edge-Triggered J- Flip-Flops with Preset, Clear, and Complementary Outputs Literature Number: SNOS278A 54LS109 54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear and Complementary Outputs


    Original     		PDF 54LS109 DM54LS109A DM74LS109A DM74LS109A SNOS278A

    54LS109

    Abstract: 54LS109DMQB 54LS109FMQB DM54LS109A DM54LS109AJ DM54LS109AW DM74LS109A DM74LS109AM DM74LS109AN J16A
    Text: 54LS109 54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs The J and K data is accepted by the flip-flop on the rising edge of the


    Original     		PDF 54LS109 DM54LS109A DM74LS109A 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109A DM74LS109AM DM74LS109AN J16A

    LS74

    Abstract: 54LS109 LS109 4 jn
    Text: MICROCIRCUIT DATA SHEET Original Creation Date: 04/24/98 Last Update Date: 09/14/98 Last Major Revision Date: 07/07/98 54LS109-X REV 1A0 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP General Description The 'LS109 consists of two high-speed, completely independent transition clocked


    Original     		PDF MNDM54LS109-X LS109 54LS109 DM54LS109J/883 DM54LS109W/883 MIL-STD-883, M0002951 54LS109 LS74 4 jn

    Untitled

    Abstract: No abstract text available
    Text: Z9A National SLA Semiconductor 54LS109/54LS109A/DM74LSJI09A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and


    OCR Scan     		PDF 54LS109/DM54LS109A/DM74LSJI09A

    Untitled

    Abstract: No abstract text available
    Text: LS109A National Semiconductor 54LS109/54LS109A/DM74LSJ09A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig­ gered J-K flip-flops with complementary outputs. The J and


    OCR Scan     		PDF 54LS109/DM54LS109A/DM74LSJ09A

    Untitled

    Abstract: No abstract text available
    Text: June 1989 54LS109/54LS109A/DM74LSJ109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig­ gered J-K flip-flops with complementary outputs. The J and


    OCR Scan     		PDF 54LS109/DM54LS109A/DM74LSJ109A

    Untitled

    Abstract: No abstract text available
    Text: Signetics 54LS109 Flip-Flop Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Military Logic Products DESCRIPTION Th e 5 4 L S 1 09 is a dual positive edge-trig­ gered JR-type flip-flop featuring individual J, K, Clock, S et and R eset inputs; also


    OCR Scan     		PDF 54LS109 54LSXXX 500ns 1N916 1N3064,

    Untitled

    Abstract: No abstract text available
    Text: M MOTOROLA Military 54LS109A Dual J-K Flip-Flop With Clear and Preset ELECTRICALLY TESTED PER: MIL-M-38510/30109 M The 54LS109A consists of two high-speed completely independent transition clocked J-K flip-flops. The clocking operation is independent of


    OCR Scan     		PDF 54LS109A MIL-M-38510/30109 54LS109A JM38510/30109BXA 54LS109A/BXAJC 56A-02

    54LS109

    Abstract: 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109AM DM74LS109AN J16A M16A
    Text: June 1989 54LS109/54LS109A/DM74LSjK 9A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig£ered J-K flip-flops with complementary outputs. The J and


    OCR Scan     		PDF 54LS109/DM54LS109A/DM74LSJ109A 54LS109 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109AM DM74LS109AN J16A M16A

    Untitled

    Abstract: No abstract text available
    Text: 54LS109 Signetics Flip-Flop Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Military Logic Products DESCRIPTION The 54LS109 is a dual positive edge-trig­ gered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also


    OCR Scan     		PDF 54LS109 54LS109 54LSXXX 500ns S15ns 1N916 1N3064,

    54LS109

    Abstract: 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109AN J16A M16A LS109 DM74LS109
    Text: LS109A National Semiconductor 54LS109/54LS109A/DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and


    OCR Scan     		PDF 54LS109/DM54LS109A/DM74LS109A 54LS109 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109AN J16A M16A LS109 DM74LS109

    54LS109A

    Abstract: 54LS109A/BEAJC
    Text: M MOTOROLA M ilitary 54LS109A Dual J -K Flip-Flop W ith C le ar and P reset ELECTRICALLY TESTED PER: MIL-M-38510/30109 M The 54LS109A consists of two high-speed completely independent transition clocked J-K flip-flops. The clocking operation is independent of


    OCR Scan     		PDF MIL-M-38510/30109 54LS109A 54LS109A JM38510/30109BXA 54LS109A/BXAJC 54LS109A/BEAJC

    74LS109PC

    Abstract: No abstract text available
    Text: 109 C O N N E C T IO N D IA G R A M PINOUT A /54S /74S 109 v o4LS/74LS109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N — The '109 consists of tw o high speed, com pletely indepen­ dent transition clocked J K flip-flops. The clocking operation is independent


    OCR Scan     		PDF o4LS/74LS109 54/74S 54/74LS 74LS109PC

    Untitled

    Abstract: No abstract text available
    Text: SN54109, 54LS109A, SN74109, SN74LS109A DUAL J-K POSITIVE-EDGE TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR DECEMBER 1983 - REVISED MARCH 1988 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic


    OCR Scan     		PDF SN54109, SN54LS109A, SN74109, SN74LS109A

    74s188 programming

    Abstract: 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions
    Text: The E ngineering Staff of TEXAS INSTRUMENTS INCORPORATED Semiconductor Memory Data Book y for \ T exas In Design Engineers s t r u m e n t s >le of Contents • Alphanumeric Index • GENERAL INFORMATION Selection Guides • Glossary INTERCHANGEABILITY GUIDE


    OCR Scan     		PDF 38510/MACH MIL-M-38510 74s188 programming 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions

    74LS115

    Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
    Text: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25


    OCR Scan     		PDF

    SN74ALS123

    Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
    Text: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS


    OCR Scan     		PDF MIL-M-38510 SN74ALS123 SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138

    dm8130

    Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
    Text: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408


    OCR Scan     		PDF 54H00 54L00 54LS00 54H01 54L01 54LS01 54L02 54LS02 54L03 54LS03 dm8130 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76

    DM74367

    Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
    Text: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,


    OCR Scan     		PDF

    54LS641

    Abstract: CD Octal D-type flip-flop 74LS00 QUAD 2-INPUT NAND GATE 54LS642 54LS154 74LS00 quad TTL nand gate 74ls00 NAND gate SchottkyBarrierDiode 54LS92 54LS623
    Text: MAXIMUM RATINGS Supply Voltage - Vcc T h e S e rie s 5 4 L S /7 4 L S Schottky TTL family features both Schottky-barrier-diode inputs and em itte r inputs and u tilizes full Schottky-barrier-diode clamping to achieve speeds com parable to Series 54/74 at one-fifth of the


    OCR Scan     		PDF 54LS00 74LS00 24-LEAD 20-LEAD 54LS390/E 54LS393/C 54LS395A/E 54LS445/E 54LS490/E 54LS533/R 54LS641 CD Octal D-type flip-flop 74LS00 QUAD 2-INPUT NAND GATE 54LS642 54LS154 74LS00 quad TTL nand gate 74ls00 NAND gate SchottkyBarrierDiode 54LS92 54LS623

    bipolar PROM

    Abstract: plhs18p8 S4LS04 82HS641 PLHS18 54175 82s137a 82S191 68172 54F04
    Text: Signetics I Alphanumeric I Index Military Products H LM119 LM124 LM139 Vol. 1 17 Dual Voltage Comparator Vol.2 22 26 26 Low Power Quad Op Amp LM139A Qual Voltage Comparator Qual Voltage Comparator PLC18V8Z Zero Standby Power Universal PAL -Type Device PLC415


    OCR Scan     		PDF LM119 LM124 LM139 LM139A PLC18V8Z PLC415 PLHS18P8A PLHS473 PLHS501 PLS105 bipolar PROM plhs18p8 S4LS04 82HS641 PLHS18 54175 82s137a 82S191 68172 54F04

    LG color tv Circuit Diagram schematics

    Abstract: texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243
    Text: IN D EXES Alphanumeric • Functional/Selection Guide IN T E R C H A N G E A B ILIT Y GUIDE G E N E R A L INFORM ATION O RD ERIN G IN STRUCTIO N S AND M ECH A N ICA L D A TA 5 4 /7 4 FA M ILIE S OF CO M PATIBLE T T L C IR C U ITS 54/74 F A M IL Y SSI C IR C U ITS


    OCR Scan     		PDF MIL-M-38510 38510/MACH 3186J Z501201 Z012510 Z011510 D022110 D022130 D021110 D021130 LG color tv Circuit Diagram schematics texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243

    54LS109

    Abstract: 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109A DM74LS109AN J16A M16A
    Text: E M IC D N D U C T O R t General Description This device contains tw o independent positive-edge-triggered J-K flip-flops w ith com plem entary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. T he triggering occurs at a vo lt­


    OCR Scan     		PDF DM74LS109A 16-Lead DM74LS109AN 54LS109FMQB DM54LS109AW 54LS109 54LS109DMQB DM54LS109AJ DM74LS109A J16A M16A

    SN7401

    Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
    Text: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package


    OCR Scan     		PDF 24-lead SN74S474 SN54S475 SN74S475 SN54S482 SN74S482 LCC4270 SN54490 SN74490 SN54LS490 SN7401 sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c