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onsemi 74F113PC IC FF JK TYPE DUAL 1BIT 14DIP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	74F113PC	Tube			25	1 - 10 - 100 $0.472 1000 $0.472 10000 $0.472	Buy Now
Fairchild Semiconductor Corporation 74F113PC
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Bristol Electronics	74F113PC		16			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Quest Components	74F113PC		114			1 $0.645 10 $0.516 100 $0.387 1000 $0.387 10000 $0.387	Buy Now
ComSIT USA	74F113PC					1 - 10 - 100 - 1000 - 10000 -	Get Quote
Fairchild Semiconductor Corporation 74F113PCQR F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Quest Components	74F113PCQR		769			1 $1.35 10 $1.35 100 $0.63 1000 $0.5625 10000 $0.5625	Buy Now
National Semiconductor Corporation 74F113PC IC,FLIP-FLOP,DUAL,J/K TYPE,F-TTL,DIP,14PIN,PLASTIC
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Quest Components	74F113PC		574			1 $0.387 10 $0.387 100 $0.258 1000 $0.1806 10000 $0.1806	Buy Now
	74F113PC		79			1 $0.645 10 $0.516 100 $0.387 1000 $0.387 10000 $0.387	Buy Now
	74F113PC		3			1 $0.942 10 $0.942 100 $0.942 1000 $0.942 10000 $0.942	Buy Now

74F113PC Datasheets (7)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
74F113PC		Fairchild Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop		Original	PDF
74F113PC		Fairchild Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop		Original	PDF
74F113PC		National Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop		Original	PDF
74F113PC		Fairchild Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop		Scan	PDF
74F113PC		Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.		Historical	PDF
74F113PCQR		Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.		Historical	PDF
74F113PCX		Fairchild Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop		Original	PDF

74F113PC Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
74F113 Abstract: 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A Text: Revised July 1999 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as long as	Original	74F113 74F113 74F113SC 14-Lead 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A	PDF
E 94733 Abstract: E 94733 3 74F113 74F113PC 74F113SC 74F113SJ C1995 F113 M14A M14D Text: 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’F113 offers individual J K Set and Clock inputs When the clock goes HIGH the inputs are enabled and data may be entered The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flip-flop will	Original	74F113 74F113PC 74F113SC 14-Lead E 94733 E 94733 3 74F113 74F113PC 74F113SC 74F113SJ C1995 F113 M14A M14D	PDF
74F113 Abstract: M14A M14D MS-001 N14A 74F113PC 74F113SC 74F113SJ Text: Revised September 2000 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs	Original	74F113 74F113 74F113SC 14-Lead M14A M14D MS-001 N14A 74F113PC 74F113SC 74F113SJ	PDF
74F113 Abstract: F113 M14A M14D N14A 74F113PC 74F113SC 74F113SJ Text: 74F113 Dual JK Negative Edge-Triggered Flip-Flop Asynchronous input: General Description The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be	Original	74F113 74F113PC 14-Lead 74F113 F113 M14A M14D N14A 74F113PC 74F113SC 74F113SJ	PDF
220v AC voltage stabilizer schematic diagram Abstract: BA 49182 RJh 3047 rjh 3047 equivalent a1458 opto philips ecg master replacement guide MOSFET, rjh 3077 sc1097 philips ecg semiconductors master replacement guide Electronic ballast 40W using 13005 transistor Text: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 2-6 Fiber Optic Connectors and Accessories . . . . . . . . . . . See Page 121 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 10-122 Fiber Optic Cable, Connectors, and Accessories . . . . . . See Pages 118-122	Original	P390-ND P465-ND P466-ND P467-ND LNG901CF9 LNG992CFBW LNG901CFBW LNG91LCFBW 220v AC voltage stabilizer schematic diagram BA 49182 RJh 3047 rjh 3047 equivalent a1458 opto philips ecg master replacement guide MOSFET, rjh 3077 sc1097 philips ecg semiconductors master replacement guide Electronic ballast 40W using 13005 transistor	PDF
Untitled Abstract: No abstract text available Text: S E M IC O N D U C T O R tm 74F113 Dual JK Negative Edge-Triggered Flip-Flop Asynchronous input: G en eral D escrip tio n The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be	OCR Scan	74F113	PDF
KL SN 102 Abstract: 74F113 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A Text: Revised July 1999 E M IC D N D U C T D R T M 74F113 Dual JK Negative Edge-Triggered Flip-Flop transferred to the outputs on the falling edge of the clock pulse. General Description T he 74F113 offers individual J, K, Set and C lo ck inputs. W hen the clock goes H IGH the inputs are enabled and	OCR Scan	74F113 74F113 KL SN 102 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A	PDF
74F161 PC Abstract: 74F163PC 74f500 74f558 74F164PC 74F548PC 74F138d 74F547PC transistor f630 74F253DC Text: F a ir c h ild A d v a n c e d S c h o t t k y T L $ 3. HANDLING PRECAUTIONS FOR SEMICONDUCTOR COMPONENTS The follow ing handling precautions should be observed for oxide isolation, shallow junction processed parts, such as FAST or 100K ECL: 1. All Fairchild devices are shipped in conducting foam or anti	OCR Scan		PDF
Untitled Abstract: No abstract text available Text: S E M IC O N D U C T O R tm 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description Asynchronous input: The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be	OCR Scan	74F113 74F113PC 14-Lead	PDF
Untitled Abstract: No abstract text available Text: E M ¡ C O N D U C T O R Revised July 1999 TM 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs	OCR Scan	74F113 74F113SC 74F113SJ 74F113PC	PDF
Untitled Abstract: No abstract text available Text: c*> National Semiconductor 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description Asynchronous input: LOW input to 3 q sets Q to HIGH level Set is independent of clock The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may	OCR Scan	74F113 74F113PC 74F113SC 74F113SJ	PDF
Untitled Abstract: No abstract text available Text: Semiconductor August 1995 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be	OCR Scan	74F113 74F113PC 14-Leasafety	PDF
E 94733 Abstract: No abstract text available Text: &N a t i o n a I S e m i c o n d u c t o r 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be	OCR Scan	74F113 bS01122 E 94733	PDF