74F113SC Search Results

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Rochester Electronics LLC 74F113SCX J-K FLIP-FLOP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	74F113SCX	Bulk			2,219	1 - 10 - 100 - 1000 - 10000 $0.14	Buy Now
National Semiconductor Corporation 74F113SC
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Bristol Electronics	74F113SC		165			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Quest Components	74F113SC		133			1 $0.609 10 $0.5075 100 $0.406 1000 $0.406 10000 $0.406	Buy Now
Fairchild Semiconductor Corporation 74F113SCX
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Quest Components	74F113SCX		1,312			1 $0.77 10 $0.77 100 $0.231 1000 $0.154 10000 $0.154	Buy Now
Rochester Electronics	74F113SCX		47,277		1	1 $0.13 10 $0.13 100 $0.1222 1000 $0.1105 10000 $0.1105	Buy Now
Fairchild Semiconductor Corporation 74F113SC IC,FLIP-FLOP,DUAL,J/K TYPE,F-TTL,SOP,14PIN,PLASTIC
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Quest Components	74F113SC		100			1 $0.945 10 $0.756 100 $0.4725 1000 $0.4725 10000 $0.4725	Buy Now
	74F113SC		28			1 $0.945 10 $0.756 100 $0.4725 1000 $0.4725 10000 $0.4725	Buy Now

74F113SC Datasheets (7)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
74F113SC		Fairchild Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop		Original	PDF
74F113SC		Fairchild Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop		Original	PDF
74F113SC		National Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop		Original	PDF
74F113SC		Fairchild Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop		Scan	PDF
74F113SC		Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.		Historical	PDF
74F113SCX		Fairchild Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop		Original	PDF
74F113SCX		Fairchild Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop		Original	PDF

74F113SC Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
74F113 Abstract: 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A Text: Revised July 1999 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as long as	Original	74F113 74F113 74F113SC 14-Lead 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A	PDF
TTL 1-of-8 encoder Abstract: 74LS 2-input OR gate 74LS series logic gates 3 input nand gate 74LS series logic gates 3 input or gate 74F374SC Text: 1/2 TTL LOGIC 74F SERIES 74F SERIES • 74F: EXCELLENT SPEED/POWER CONSUMPTION COMBINATION Part Number Description SQP £ ea. Gates & Inverters 74F00SC Quad 2-Input NAND Gate 74F02SC Quad 2-Input NOR Gate 74F04SC Hex Inverter 74F08SC Quad 2-Input AND Gate	Original	74F164ASC 74F194SC 74F299SC 74F350SC 74F378SC 74F379SC 74F398SC 74F399SC 74F675ASC 74F676SC TTL 1-of-8 encoder 74LS 2-input OR gate 74LS series logic gates 3 input nand gate 74LS series logic gates 3 input or gate 74F374SC	PDF
E 94733 Abstract: E 94733 3 74F113 74F113PC 74F113SC 74F113SJ C1995 F113 M14A M14D Text: 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’F113 offers individual J K Set and Clock inputs When the clock goes HIGH the inputs are enabled and data may be entered The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flip-flop will	Original	74F113 74F113PC 74F113SC 14-Lead E 94733 E 94733 3 74F113 74F113PC 74F113SC 74F113SJ C1995 F113 M14A M14D	PDF
74F113 Abstract: M14A M14D MS-001 N14A 74F113PC 74F113SC 74F113SJ Text: Revised September 2000 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs	Original	74F113 74F113 74F113SC 14-Lead M14A M14D MS-001 N14A 74F113PC 74F113SC 74F113SJ	PDF
74F113 Abstract: F113 M14A M14D N14A 74F113PC 74F113SC 74F113SJ Text: 74F113 Dual JK Negative Edge-Triggered Flip-Flop Asynchronous input: General Description The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be	Original	74F113 74F113PC 14-Lead 74F113 F113 M14A M14D N14A 74F113PC 74F113SC 74F113SJ	PDF
Untitled Abstract: No abstract text available Text: S E M IC O N D U C T O R tm 74F113 Dual JK Negative Edge-Triggered Flip-Flop Asynchronous input: G en eral D escrip tio n The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be	OCR Scan	74F113	PDF
KL SN 102 Abstract: 74F113 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A Text: Revised July 1999 E M IC D N D U C T D R T M 74F113 Dual JK Negative Edge-Triggered Flip-Flop transferred to the outputs on the falling edge of the clock pulse. General Description T he 74F113 offers individual J, K, Set and C lo ck inputs. W hen the clock goes H IGH the inputs are enabled and	OCR Scan	74F113 74F113 KL SN 102 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A	PDF
Untitled Abstract: No abstract text available Text: S E M IC O N D U C T O R tm 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description Asynchronous input: The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be	OCR Scan	74F113 74F113PC 14-Lead	PDF
Untitled Abstract: No abstract text available Text: E M ¡ C O N D U C T O R Revised July 1999 TM 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs	OCR Scan	74F113 74F113SC 74F113SJ 74F113PC	PDF
Untitled Abstract: No abstract text available Text: c*> National Semiconductor 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description Asynchronous input: LOW input to 3 q sets Q to HIGH level Set is independent of clock The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may	OCR Scan	74F113 74F113PC 74F113SC 74F113SJ	PDF
Untitled Abstract: No abstract text available Text: Semiconductor August 1995 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be	OCR Scan	74F113 74F113PC 14-Leasafety	PDF
E 94733 Abstract: No abstract text available Text: &N a t i o n a I S e m i c o n d u c t o r 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be	OCR Scan	74F113 bS01122 E 94733	PDF