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    74LVX112SJ Price and Stock

    Rochester Electronics LLC 74LVX112SJ

    IC FF JK TYPE DUAL 1BIT 16SOP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey 74LVX112SJ Tube 1,268
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    • 10000 $0.24
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    Fairchild Semiconductor Corporation 74LVX112SJ

    J-K Flip-Flop, LV/LV-A/LVX/H Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16 '
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Rochester Electronics 74LVX112SJ 12,126 1
    • 1 $0.2275
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    • 100 $0.2139
    • 1000 $0.1934
    • 10000 $0.1934
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    74LVX112SJ Datasheets (6)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74LVX112SJ Fairchild Semiconductor Low Voltage Dual J-K Flip-Flops with Preset and Clear Original PDF
    74LVX112SJ Fairchild Semiconductor Logic - Flip Flops, Integrated Circuits (ICs), IC JK TYPE NEG TRG DUAL 16SOP Original PDF
    74LVX112SJ National Semiconductor Low Voltage Dual J-K Flip-Flops with Preset and Clear Original PDF
    74LVX112SJX Fairchild Semiconductor Low Voltage Dual J-K Flip-Flops with Preset and Clear Original PDF
    74LVX112SJX Fairchild Semiconductor Low Voltage Dual J-K Flip-Flops with Preset and Clear Original PDF
    74LVX112SJX National Semiconductor Low Voltage Dual J-K Flip-Flops with Preset and Clear Original PDF

    74LVX112SJ Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74LVX112

    Abstract: 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16
    Text: 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK and outputs (Q, Q). These devices are edge sensitive and change states synchronously on the negative going transition of the clock pulse. Triggering occurs at a voltage level of


    Original     		PDF 74LVX112 LVX112 74LVX112 74LVX112M 74LVX112MTC 74LVX112SJ M16A M16D MTC16

    5555 FAIRCHILD optocoupler

    Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
    Text: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference


    Original     		PDF SCYB017A A010203 5555 FAIRCHILD optocoupler MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N

    74LVX112

    Abstract: 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16
    Text: Revised December 2003 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK and outputs (Q, Q). These devices are edge sensitive and


    Original     		PDF 74LVX112 LVX112 74LVX112 74LVX112M 74LVX112MTC 74LVX112SJ M16A M16D MTC16

    74LVX112

    Abstract: 74LVX112M 74LVX112MTC 74LVX112MTCX 74LVX112MX 74LVX112SJ 74LVX112SJX LVX112 M16A M16D
    Text: 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J K PRESET CLEAR and CLOCK and outputs (Q Q) These devices are edge sensitive and change states synchronously on the negative going transition of the clock pulse Triggering occurs at a voltage level


    Original     		PDF 74LVX112 LVX112 74LVX112 74LVX112M 74LVX112MTC 74LVX112MTCX 74LVX112MX 74LVX112SJ 74LVX112SJX M16A M16D

    MC0628R

    Abstract: 40373 74hc14n equivalent 4046 application note philips HCF4060BE HCF4017BE SN74121 application note MC74HC373DW mc0628 HCF4053BE
    Text: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference


    Original     		PDF SCYB017A T74ALVC32374 74CBTLV16211 SN74CBTD16211 SN74SSTV16859 SN74CBTLV16211GRDR SN74ALVC16245AGRDR -SN74SSTV16859GKER MC0628R 40373 74hc14n equivalent 4046 application note philips HCF4060BE HCF4017BE SN74121 application note MC74HC373DW mc0628 HCF4053BE

    74LVX112

    Abstract: 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16
    Text: Revised March 1999 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK and outputs (Q, Q). These devices are edge sensitive and


    Original     		PDF 74LVX112 LVX112 74LVX112 74LVX112M 74LVX112MTC 74LVX112SJ M16A M16D MTC16

    5555 FAIRCHILD optocoupler

    Abstract: DM74LS75N MC74HC373DW 74hc14n equivalent HCF4060BE 40373 NC7S125M5X datasheet 14543 motorola 14049 CD40106BE
    Text: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference


    Original     		PDF SCYB017A A010203 5555 FAIRCHILD optocoupler DM74LS75N MC74HC373DW 74hc14n equivalent HCF4060BE 40373 NC7S125M5X datasheet 14543 motorola 14049 CD40106BE

    Untitled

    Abstract: No abstract text available
    Text: Revised March 1999 SEMICONDUCTOR TM General Description The inputs tolerate voltages up to 7V allowing the interface of 5V system s to 3V system s. Features • Input voltage level translation from 5 V -3 V ■ Ideal fo r low pow er/low noise 3.3V applications


    OCR Scan     		PDF 74LVX112 74LVX112 LVX112

    Untitled

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description Th e inputs tolerate voltages up to 7V allowing the interface of 5V system s to 3V system s. The LVX112 is a dual J-K Flip-Flop where each flip-flop has


    OCR Scan     		PDF 74LVX112 LVX112 2314-006I

    MTC 25-16

    Abstract: 74LVX112 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16
    Text: A I R C H I I- D S E M IC O N D U C T O R im 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The inputs tolerate voltages up to 7 V allowing the interface of 5V system s to 3 V system s. The LVX112 is a dual J-K Flip-Flop w here each flip-flop has


    OCR Scan     		PDF 74LVX112 LVX112 MTC 25-16 74LVX112 74LVX112M 74LVX112MTC 74LVX112SJ M16A M16D MTC16

    74LVX112

    Abstract: 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16 AD508
    Text: S E M I C O N D U C T O R Revised March 1999 TM General Description either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. The inputs tolerate voltages up to 7V allowing the interface


    OCR Scan     		PDF 74LVX112 LVX112 74LVX112 74LVX112M 74LVX112MTC 74LVX112SJ M16A M16D MTC16 AD508

    Untitled

    Abstract: No abstract text available
    Text: A I R C H October 1996 I L D Revised March 1999 S E M [CONDUCTOR TM 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK


    OCR Scan     		PDF 74LVX112 LVX112