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    modelsim SE 6.3f user guide

    Abstract: No abstract text available
    Text: 10 Gb+ Ethernet MAC IP Core User’s Guide December 2010 IPUG39_02.9 Table of Contents Chapter 1. Introduction . 4 Quick Facts . 4


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    IPUG39 E-5F900C D-2010 03L-SP1 ETHER-10G-SC-U4. modelsim SE 6.3f user guide PDF

    h945

    Abstract: H944 transistor h945 h965 h946 H948 IR1518 BCM56800 h945 transistor H808
    Text: LatticeECP3 and Broadcom 10 Gbps Physical/MAC Layer Interoperability July 2010 Technical Note TN1218 Introduction This technical note describes a Physical/MAC layer 10-Gigabit Ethernet interoperability test between a LatticeECP3 device and the Broadcom BCM56800 network switch. The test exercises the Physical/MAC layer


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    TN1218 10-Gigabit BCM56800 h945 H944 transistor h945 h965 h946 H948 IR1518 h945 transistor H808 PDF

    h946

    Abstract: H945 H944 h965 H924 h940 295050 transistor h945 H948 transistor BC rx
    Text: LatticeECP3 and Marvell 10 Gbps Physical/MAC Layer Interoperability July 2010 Technical Note TN1219 Introduction This technical note describes a Physical/MAC Layer 10-Gigabit Ethernet interoperability test between a LatticeECP3 device and the Marvell Alaska 88X2040 device. The test exercises the Physical/MAC Layer up to


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    TN1219 10-Gigabit 88X2040 h946 H945 H944 h965 H924 h940 295050 transistor h945 H948 transistor BC rx PDF

    higig2 frame format

    Abstract: "higig header" EZchip higig2 higig specification verilog code for spi4.2 to fifo higig pause frame marvell 618 datasheet pt36C 0x00900
    Text: LatticeSCM XAUI to SPI4.2 July 2008 Reference Design RD1033 Introduction The XAUI to SPI4.2 X2S4 Bridge reference design is a cost-effective system solution for bridging SPI4.2 based network processors and 10G/10G+ Ethernet switching devices. On the XAUI side, the X2S4 optionally supports the


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    RD1033 10G/10G+ 12Gbps RD1033. higig2 frame format "higig header" EZchip higig2 higig specification verilog code for spi4.2 to fifo higig pause frame marvell 618 datasheet pt36C 0x00900 PDF