CD4027BMN Search Results

CD4027BMN Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CD4027BMN		National Semiconductor	Dual J-K Master/Slave Flip-Flop with Set and Reset		Scan	PDF

CD4027BMN Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
5958 Abstract: 74LS AN-90 C1995 CD4027B CD4027BC CD4027BCJ CD4027BM CD4027BMJ J16A Text: CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description Features These dual J-K flip-flops are monolithic complementary MOS CMOS integrated circuits constructed with N- and Pchannel enhancement mode transistors Each flip-flop has	Original	CD4027BM CD4027BC 5958 74LS AN-90 C1995 CD4027B CD4027BCJ CD4027BMJ J16A	PDF
74LS Abstract: AN-90 CD4027B CD4027BC CD4027BCJ CD4027BM CD4027BMN J16A CD4027BCN Text: & February 1988 Semiconductor CD4027BM/CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset Features • Wide supply voltage range ■ High noise immunity ■ Low power TTL compatibility ■ Low power ■ Medium speed operation 3.0V to 15V 0.45 VDD typ.	OCR Scan	CD4027BM/CD4027BC 74LS AN-90 CD4027B CD4027BC CD4027BCJ CD4027BM CD4027BMN J16A CD4027BCN	PDF
Untitled Abstract: No abstract text available Text: February 1988 CD4027BM/CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description Features These dual J-K flip-flops are monolithic complementary MOS CMOS integrated circuits constructed with N- and Pchannel enhancement mode transistors. Each flip-flop has	OCR Scan	CD4027BM/CD4027BC	PDF
74LS Abstract: AN-90 CD4027B CD4027BC CD4027BCJ CD4027BM CD4027BMN J16A Text: & February 1988 Semiconductor CD4027BM/CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset Features • Wide supply voltage range ■ High noise immunity ■ Low power TTL compatibility ■ Low power ■ Medium speed operation 3.0V to 15V 0.45 VDD typ.	OCR Scan	CD4027BM/CD4027BC 74LS AN-90 CD4027B CD4027BC CD4027BCJ CD4027BM CD4027BMN J16A	PDF