CML ECL termination
Abstract: dj rm RJ12 RJ22
Text: I/O Structures and Jitter Presentation 1 RELATIVE SIGNAL SWINGS AND LEVELS PECL 4V “5V ECL” CML 3.3V 3V CML (2.5V) LVPECL 2V LVPECL LVDS -1V -2V CML (1.2V) “3V ECL” 1V 0V CML (1.8V) Referenced to Ground “2.5V ECL” ECL Older Technology - Rarely seen
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325mV
800mV
400mV
CML ECL termination
dj rm
RJ12
RJ22
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CML ECL termination
Abstract: AND8173 AND8020
Text: AND8173/D Termination and Interface of On Semiconductor ECL Devices With CML Current Mode Logic OUTPUT Structure http://onsemi.com APPLICATION NOTE By Paul Shockman Contents SECTION 1.UNLOADED CML VOLTAGE LEVELS (DC OPEN) SECTION 2.DIRECT CONNECT (DC) CML LOAD
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AND8173/D
CML ECL termination
AND8173
AND8020
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AND8020
Abstract: CML ECL termination Z0 127 TRANSISTOR equivalent
Text: AND8173/D Termination and Interface of ON Semiconductor ECL Devices With CML Current Mode Logic OUTPUT Structure http://onsemi.com APPLICATION NOTE By Paul Shockman Introduction Contents SECTION 1.UNLOADED CML VOLTAGE LEVELS (DC OPEN) SECTION 2.DIRECT CONNECT (DC) CML LOAD
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AND8173/D
AND8020
CML ECL termination
Z0 127 TRANSISTOR equivalent
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KPT21
Abstract: MC100EPT21 2x2 dfn
Text: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small
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MC100EPT21
MC100EPT21
EPT21
MC100EPT21/D
KPT21
2x2 dfn
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KPT21
Abstract: MC100EPT21 KA21
Text: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small
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MC100EPT21
MC100EPT21
EPT21
MC100EPT21/D
KPT21
KA21
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MC100EPT21DG
Abstract: No abstract text available
Text: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small
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MC100EPT21
EPT21
MC100EPT21/D
MC100EPT21DG
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KPT21
Abstract: MC100EPT21
Text: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small
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MC100EPT21
MC100EPT21
EPT21
MC100EPT21/D
KPT21
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KPT21
Abstract: MC100EPT21
Text: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small
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MC100EPT21
MC100EPT21
EPT21
MC100EPT21/D
KPT21
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KPT21
Abstract: MC100EPT21
Text: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small
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MC100EPT21
MC100EPT21
EPT21
MC100EPT21/D
KPT21
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Untitled
Abstract: No abstract text available
Text: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small
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MC100EPT21
MC100EPT21
EPT21
MC100EPT21/D
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KPT23
Abstract: EPT23 MC100EPT23 VDFN-8 mc100ept23dg
Text: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small
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MC100EPT23
MC100EPT23
EPT23
EPT23
MC100EPT23/D
KPT23
VDFN-8
mc100ept23dg
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EPT23
Abstract: KPT23 MC100EPT23 2x2 dfn
Text: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small
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MC100EPT23
MC100EPT23
EPT23
EPT23
MC100EPT23/D
KPT23
2x2 dfn
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KPT23
Abstract: EPT23 MC100EPT23
Text: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small
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MC100EPT23
MC100EPT23
EPT23
EPT23
MC100EPT23/D
KPT23
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Untitled
Abstract: No abstract text available
Text: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small
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MC100EPT23
MC100EPT23
EPT23
EPT23
MC100EPT23/D
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Untitled
Abstract: No abstract text available
Text: NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Description The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL Positive ECL , CML, or LVDS. The
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NB7L32M
14GHz
NB7L32M
NB7L32Mâ
NB7L32M/D
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Untitled
Abstract: No abstract text available
Text: NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Description The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL Positive ECL , CML, or LVDS. The
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NB7L32M
14GHz
NB7L32M/D
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485G
Abstract: NB7L32M
Text: NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Description The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL Positive ECL , CML, or LVDS. The
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NB7L32M
14GHz
NB7L32M
NB7L32M/D
485G
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CML ECL termination
Abstract: MC100EP16 MC100EP16F MC100EP16VS MC100EP16VT MC100LVEP16 MC10EP16 MC10EP16T MC10LVEP16 NBSG16
Text: SGD508/D Jan-2002 Rev 0 1 to 12 GHz Differential Receiver/Drivers Bandwidth GHz Gain Input Termination (50Ω) Open Input Default State (D, D) Input Level Output Level Output Enable LOW, HIGH ECL, CMOS, CML, LVDS RSECL(3) No 1 FCBGA 16 Yes(1) LOW, HIGH ECL, CMOS,
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SGD508/D
Jan-2002
ONS81478-0
r14525
CML ECL termination
MC100EP16
MC100EP16F
MC100EP16VS
MC100EP16VT
MC100LVEP16
MC10EP16
MC10EP16T
MC10LVEP16
NBSG16
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package marking 504c
Abstract: ICS853S 853S310CVILF
Text: Low Skew, 1-to-8 Differential-to3.3V LVPECL/ECL Fanout Buffer ICS853S310I DATA SHEET General Description Features The ICS853S310I is a low skew, high performance 1-to-8 Differential-to-3.3V LVPECL/ECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept LVPECL, LVDS, CML and SSTL
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ICS853S310I
ICS853S310I
package marking 504c
ICS853S
853S310CVILF
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Untitled
Abstract: No abstract text available
Text: Low Skew, 1-to-8 Differential-to3.3V LVPECL/ECL Fanout Buffer ICS853S310I DATA SHEET General Description Features The ICS853S310I is a low skew, high performance 1-to-8 Differential-to-3.3V LVPECL/ECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept LVPECL, LVDS, CML and SSTL
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ICS853S310I
ICS853S310I
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Untitled
Abstract: No abstract text available
Text: Ultrafast SiGe Voltage Comparators ADCMP580/ADCMP581/ADCMP582 FEATURES FUNCTIONAL BLOCK DIAGRAM VCCI VTP TERMINATION VP NONINVERTING INPUT VN INVERTING INPUT VCCO ADCMP580/ ADCMP581/ ADCMP582 Q OUTPUT CML/ECL/ PECL Q OUTPUT VEE VTN TERMINATION LE INPUT HYS
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ADCMP580/ADCMP581/ADCMP582
ADCMP580/
ADCMP581/
ADCMP582
16-Lead
CP-16-3
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ADCMP580
Abstract: ADCMP581 ADCMP582 MO-220-VEED-2 PRBS31 ADCMP582BCP-R2 CP-16-3 VCCO11
Text: Ultrafast SiGe Voltage Comparators ADCMP580/ADCMP581/ADCMP582 FEATURES FUNCTIONAL BLOCK DIAGRAM VCCI VTP TERMINATION VP NONINVERTING INPUT VN INVERTING INPUT VCCO ADCMP580/ ADCMP581/ ADCMP582 Q OUTPUT CML/ECL/ PECL Q OUTPUT VEE VTN TERMINATION LE INPUT HYS
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ADCMP580/ADCMP581/ADCMP582
ADCMP580/
ADCMP581/
ADCMP582
16-Lead
CP-16-3
ADCMP580
ADCMP581
ADCMP582
MO-220-VEED-2
PRBS31
ADCMP582BCP-R2
CP-16-3
VCCO11
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maxim 872
Abstract: AN872 APP872 MAX9110 MAX9111 MAX9150 CML ECL termination
Text: Maxim > App Notes > BASESTATIONS / WIRELESS INFRASTRUCTURE INTERFACE CIRCUITS HIGH-SPEED INTERCONNECT Keywords: LVDS, low voltage, differential signaling signalling, lvds, EIA/TIA-644, high speed, clock distribution, ECL, PECL, CML, low noise emission, low power
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EIA/TIA-644,
EIA/TAI-644
com/an872
MAX9110:
MAX9111:
MAX9150:
AN872,
APP872,
Appnote872,
maxim 872
AN872
APP872
MAX9110
MAX9111
MAX9150
CML ECL termination
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TIA-644
Abstract: AN872 APP872 MAX9110 MAX9111 MAX9150
Text: Maxim > App Notes > Basestations/Wireless Infrastructure High-Speed Interconnect Interface Circuits Keywords: LVDS, low voltage, differential signaling, lvds, EIA/TIA-644, high speed, clock distribution, ECL, PECL, CML, low noise emission, low power Dec 13, 2001
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EIA/TIA-644,
EIA/TIA-644
MAX9110:
MAX9111:
MAX9150:
com/an872
AN872,
APP872,
Appnote872,
TIA-644
AN872
APP872
MAX9110
MAX9111
MAX9150
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