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Untitled Abstract: No abstract text available Text: THIS SPEC IS OBSOLETE Spec No: 001-06582 Spec Title: CY7C1161V18/CY7C1176V18/CY7C1163V18/ CY7C1165V18, 18-MBIT QDR TM -II+ SRAM 4-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) Sunset Owner: Jayasree Nayar (njy) Replaced by: NONE CY7C1161V18, CY7C1176V18	Original	CY7C1161V18/CY7C1176V18/CY7C1163V18/ CY7C1165V18, 18-MBIT CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18	PDF
Untitled Abstract: No abstract text available Text: CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit CY7C1161V18, CY7C1176V18, CY7C1163V18, CY7C1165V18	PDF
CY7C1161V18 Abstract: CY7C1163V18 CY7C1165V18 CY7C1176V18 Text: CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit CY7C1161V18 CY7C1163V18 CY7C1165V18 CY7C1176V18	PDF
Untitled Abstract: No abstract text available Text: CY7C1176V18 CY7C1163V18 CY7C1165V18 PRELIMINARY 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit CY7C1176V18/CY7C1163V18/CY7C1165V18 CY7C1176BV18	PDF
CY7C1161V18 Abstract: CY7C1163V18 CY7C1165V18 CY7C1176V18 Text: CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 18-Mbit CY7C1161V18 CY7C1163V18 CY7C1165V18 CY7C1176V18	PDF
Untitled Abstract: No abstract text available Text: CY7C1163V18 CY7C1165V18 PRELIMINARY 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1163V18 CY7C1165V18 18-Mbit	PDF