Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    CY7C1368C Search Results

    SF Impression Pixel

    CY7C1368C Price and Stock

    Rochester Electronics LLC CY7C1368C-166AXC

    IC SRAM 8MBIT PARALLEL 100TQFP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1368C-166AXC Tray 31
    • 1 -
    • 10 -
    • 100 $9.88
    • 1000 $9.88
    • 10000 $9.88
    		Buy Now

    Cypress Semiconductor CY7C1368C-166AXC

    CY7C1368C-166AXC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Verical CY7C1368C-166AXC 1,351 33
    • 1 -
    • 10 -
    • 100 $11.1625
    • 1000 $10.1
    • 10000 $10.1
    		Buy Now
    CY7C1368C-166AXC 73 33
    • 1 -
    • 10 -
    • 100 $11.1625
    • 1000 $10.1
    • 10000 $10.1
    		Buy Now
    CY7C1368C-166AXC 64 33
    • 1 -
    • 10 -
    • 100 $11.1625
    • 1000 $10.1
    • 10000 $10.1
    		Buy Now
    Rochester Electronics CY7C1368C-166AXC 1,742 1
    • 1 $9.5
    • 10 $9.5
    • 100 $8.93
    • 1000 $8.08
    • 10000 $8.08
    		Buy Now

    CY7C1368C Datasheets (5)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1368C Cypress Semiconductor 9-Mbit (256K x 32) Pipelined DCD Sync SRAM Original PDF
    CY7C1368C-166AJXC Cypress Semiconductor 9-Mbit (256K x 32) Pipelined DCD Sync SRAM Original PDF
    CY7C1368C-166AXC Cypress Semiconductor 9-Mbit (256K x 32) Pipelined DCD Sync SRAM Original PDF
    CY7C1368C-166AXCT Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 8MBIT 166MHZ 100LQFP Original PDF
    CY7C1368C-166AXI Cypress Semiconductor 9-Mbit (256K x 32) Pipelined DCD Sync SRAM Original PDF

    CY7C1368C Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: CY7C1368C 9-Mbit 256 K x 32 Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state


    Original     		PDF CY7C1368C CY7C1368C

    Untitled

    Abstract: No abstract text available
    Text: CY7C1368C 9-Mbit 256 K x 32 Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM Features Functional Description[1] • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state


    Original     		PDF CY7C1368C CY7C1368C

    Untitled

    Abstract: No abstract text available
    Text: CY7C1368C PRELIMINARY 9-Mb 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture


    Original     		PDF CY7C1368C 32-bit 250-MHz 200-MHz 166-MHz CY7C1368C

    CY7C1368C

    Abstract: No abstract text available
    Text: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture


    Original     		PDF CY7C1368C 32-bit 250-MHz CY7C1368C

    CY7C1368C

    Abstract: No abstract text available
    Text: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture


    Original     		PDF CY7C1368C 32-bit 250-MHz CY7C1368C

    CY7C1368C

    Abstract: No abstract text available
    Text: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation ■ Optimal for performance (Double-Cycle deselect) ❐ Depth expansion without wait state ■ 256K x 32-bit common I/O architecture


    Original     		PDF CY7C1368C 32-bit 250-MHz CY7C1368C

    Untitled

    Abstract: No abstract text available
    Text: CY7C1368C PRELIMINARY 9-Mb 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture


    Original     		PDF CY7C1368C 32-bit 250-MHz 200-MHz 166-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1368C PRELIMINARY 9-Mb 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture


    Original     		PDF CY7C1368C 32-bit 250-MHz 200-MHz 166-MHz

    Untitled

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No:38-05686 Spec Title:CY7C1368C 9-MBIT 256 K X 32 PIPELINED DCD SYNC SRAM Sunset Owner:Jayasree Nayar (NJY) Replaced by: None CY7C1368C 9-Mbit (256 K x 32) Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM


    Original     		PDF CY7C1368C CY7C1368C 32-bit 250-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture


    Original     		PDF CY7C1368C 32-bit 250-MHz 200-MHz 166-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture


    Original     		PDF CY7C1368C 32-bit 250-MHz 200-MHz 166-MHz

    FSQ510 Equivalent

    Abstract: BTA12 6008 bta16 6008 ZIGBEE interface with AVR ATmega16 Precision triac control thermostat thyristor t 558 f eupec gw 5819 diode transistor a564 A564 transistor BSM25GP120 b2
    Text: SEMICONDUCTORS MCU/MPU/DSP Atmel. . . . . . . . . 167, 168, 169, 170, 171, 172 Blackhawk. . . . . . . . . . . . . . . . . . . . . . . . . 173 Cyan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Cypress. . . . . . . . . . . . . . . 175, 176, 177, 178


    Original     		PDF GP-20) FSQ510 Equivalent BTA12 6008 bta16 6008 ZIGBEE interface with AVR ATmega16 Precision triac control thermostat thyristor t 558 f eupec gw 5819 diode transistor a564 A564 transistor BSM25GP120 b2

    CY7C1338-100AXC

    Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
    Text: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12


    Original     		PDF CY7C1019BV33-15VC GS71108AJ-12 CY7C1019BV33-15VXC GS71108AGJ-12 CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12 CY7C1019CV33-10VC GS71108AJ-10 CY7C1338-100AXC gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC