CY7C136B
Abstract: No abstract text available
Text: CY7C1360B CY7C1362B PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM Features All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock.
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Original
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CY7C1360B
CY7C1362B
36/512K
250-MHz
200-MHz
166-MHz
100-pin
119-Ball
165-Ball
CY7C1360B/CY7C1362B
CY7C136B
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1366B CY7C1367B PRELIMINARY 256K x 36/512K x 18 Pipelined Double-cycle Deselect SRAM Features • Supports bus operation up to 250 MHz — Available speed grades are 250, 200, and 166 MHz • Fully registered inputs and outputs for pipelined operation
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Original
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CY7C1366B
CY7C1367B
36/512K
100-pin
119-Ball
165-Ball
CY7C1366B/CY7C1367B
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PDF
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CY7C1366B
Abstract: CY7C1367B
Text: CY7C1366B CY7C1367B PRELIMINARY 256K x 36/512K x 18 Pipelined Double-cycle Deselect SRAM Features • Supports bus operation up to 250 MHz — Available speed grades are 250, 200, and 166 MHz • Fully registered inputs and outputs for pipelined operation
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Original
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CY7C1366B
CY7C1367B
36/512K
100-pin
119-Ball
165-Ball
CY7C1366B/CY7C1367B
CY7C1366B
CY7C1367B
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PDF
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